Scalehls: A new scalable high-level synthesis framework on multi-level intermediate representation

H Ye, C Hao, J Cheng, H Jeong… - … symposium on high …, 2022 - ieeexplore.ieee.org
High-level synthesis (HLS) has been widely adopted as it significantly improves the
hardware design productivity and enables efficient design space exploration (DSE). Existing …

Data analysis and statistics: an expository overview

JW Tukey, MB Wilk - Proceedings of the November 7-10, 1966, fall joint …, 1966 - dl.acm.org
DATA ANALYSIS AND STATISTICS: AN EXPOSITORY OVERVIEW* Page 1 DATA ANALYSIS
AND STATISTICS: AN EXPOSITORY OVERVIEW* JW Tukey and MB Wilk Princeton University …

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

D Chen, J Cong, S Gurumani, W Hwu… - IET Cyber‐Physical …, 2016 - Wiley Online Library
The rise of the Internet of Things has led to an explosion of sensor computing platforms. The
complexity and applications of IoT devices range from simple devices in vending machines …

PowerSyn: A logic synthesis framework with early power optimization

S Zou, J Zhang, B Shi, G Luo - IEEE Transactions on Computer …, 2023 - ieeexplore.ieee.org
Power is a great concern in integrated circuits (ICs) design flow, especially in portable
devices. As an early stage in electronic design automation (EDA), logic synthesis can …

High-level synthesis with timing-sensitive information flow enforcement

Z Jiang, S Dai, GE Suh, Z Zhang - Proceedings of the International …, 2018 - dl.acm.org
Specialized hardware accelerators are being increasingly integrated into today's computer
systems to achieve improved performance and energy efficiency. However, the resulting …

Audio DSP to FPGA Compilation: The Syfala Toolchain Approach

M Popoff, R Michon, T Risset, P Cochard, S Letz… - 2023 - inria.hal.science
The implementation of real-time audio Digital Signal Processing (DSP) on FPGA has been
extensively studied in the past. Up to now, Audio IPs were designed either “by hand” in …

A scalable approach to exact resource-constrained scheduling based on a joint SDC and SAT formulation

S Dai, G Liu, Z Zhang - Proceedings of the 2018 ACM/SIGDA …, 2018 - dl.acm.org
Despite increasing adoption of high-level synthesis (HLS) for its design productivity
advantage, success in achieving high quality-of-results out-of-the-box is often hindered by …

SoC design with HW/SW co-design methodology for wireless communication system

N Surantha, N Sutisna, Y Nagao… - 2017 17th International …, 2017 - ieeexplore.ieee.org
The rapid evolution and the popularity of wireless devices among worldwide users has
made wireless communication as one of the main market of system-on-chip (SoC) …

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

A Qamar, FB Muslim, J Iqbal, L Lavagno - Microprocessors and …, 2017 - Elsevier
The abstraction level for digital designs is rising from Register Transfer Level (RTL) to
algorithmic untimed or transaction-based, followed by an automated high-level synthesis …

New advances of high-level synthesis for efficient and reliable hardware design

K Campbell, W Zuo, D Chen - Integration, 2017 - Elsevier
The spectacular CMOS technology scaling will continue to evolve and dominate the
semiconductor industry. This will lead to tens of billions of transistors integrated on a single …