Pushing the level of abstraction of digital system design: A survey on how to program fpgas

ED Sozzo, D Conficconi, A Zeni, M Salaris… - ACM Computing …, 2022 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototy**, telecommunications …

Programming and synthesis for software-defined FPGA acceleration: status and future prospects

YH Lai, E Ustun, S **ang, Z Fang, H Rong… - ACM Transactions on …, 2021 - dl.acm.org
FPGA-based accelerators are increasingly popular across a broad range of applications,
because they offer massive parallelism, high energy efficiency, and great flexibility for …

Virtualizing FPGAs in the cloud

Y Zha, J Li - Proceedings of the Twenty-Fifth International …, 2020 - dl.acm.org
Field-Programmable Gate Arrays (FPGAs) have been integrated into the cloud infrastructure
to enhance its computing performance by supporting on-demand acceleration. However …

Yosys+ nextpnr: an open source framework from verilog to bitstream for commercial fpgas

D Shah, E Hung, C Wolf, S Bazanski… - 2019 IEEE 27th …, 2019 - ieeexplore.ieee.org
This paper introduces a fully free and open source software (FOSS) architecture-neutral
FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement …

RapidStream: Parallel physical implementation of FPGA HLS designs

L Guo, P Maidee, Y Zhou, C Lavin, J Wang… - Proceedings of the …, 2022 - dl.acm.org
FPGAs require a much longer compilation cycle than conventional computing platforms like
CPUs. In this paper, we shorten the overall compilation time by co-optimizing the HLS …

Flexible communication avoiding matrix multiplication on FPGA with high-level synthesis

J de Fine Licht, G Kwasniewski, T Hoefler - Proceedings of the 2020 …, 2020 - dl.acm.org
Data movement is the dominating factor affecting performance and energy in modern
computing systems. Consequently, many algorithms have been developed to minimize the …

SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs

KE Murray, MA Elgammal, V Betz, T Ansell… - IEEE Micro, 2020 - ieeexplore.ieee.org
As the benefits of Moore's Law diminish, computing performance, and efficiency gains are
increasingly achieved through specializing hardware to a domain of computation. However …

Power-hammering through glitch amplification–attacks and mitigation

K Matas, TM La, KD Pham… - 2020 IEEE 28th Annual …, 2020 - ieeexplore.ieee.org
Recent work on FPGA hardware security showed a substantial potential risk through power-
hammering, which uses high switching activity in order to create excessive dynamic power …

Reconfigurable architectures: The shift from general systems to domain specific solutions

E D'Arnese, D Conficconi, MD Santambrogio… - … : From Devices to …, 2022 - Springer
Reconfigurable computing is an expanding field that, during the last decades, has evolved
from a relatively closed community, where hard skilled developers deployed high …

RWRoute: An open-source timing-driven router for commercial FPGAs

Y Zhou, P Maidee, C Lavin, A Kaviani… - ACM Transactions on …, 2021 - dl.acm.org
One of the key obstacles to pervasive deployment of FPGA accelerators in data centers is
their cumbersome programming model. Open source tooling is suggested as a way to …