Time-to-digital converters (TDCs) are increasingly used as building blocks in biomedical
imaging, digital communication, and measurement instrumentation systems. When …

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …

A new and innovative paradigm for RF frequency synthesis and wireless transmitter design
Learn the techniques for designing and implementing an all-digital RF frequency …

This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop
(PLL) is proposed. The design procedure is based on the analogy between a type-II second …

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …

A fully digital frequency synthesizer for RF wireless applications has recently been
proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency …

RF and Microwave Transmitter Design is unique in its coverage of both historical transmitter
design and cutting edge technologies. This text explores the results of well-known and new …

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …

A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented
which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop …