A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS
T Jiang, W Liu, FY Zhong, C Zhong… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
A single-channel, asynchronous successive-approximation (SA) ADC with improved
feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure …
feedback delay is fabricated in 40 nm CMOS. Compared with a conventional SAR structure …
A near-threshold, 0.16 nJ/b OOK-transmitter with 0.18 nJ/b noise-cancelling super-regenerative receiver for the medical implant communications service
A 0.16 nJ/b MICS transmitter and 0.18 nJ/b super-regenerative receiver are demonstrated,
where each is specifically designed to operate in the near-threshold region. The low-VDD …
where each is specifically designed to operate in the near-threshold region. The low-VDD …
A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O transceiver in 65 nm CMOS
A low-power forwarded-clock I/O transceiver architecture is presented that employs a high
degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage …
degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage …
A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method
This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap
decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB …
decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB …
A wideband injection locked quadrature clock generation and distribution technique for an energy-proportional 16–32 Gb/s optical receiver in 28 nm FDSOI CMOS
M Raj, S Saeedi, A Emami - IEEE Journal of Solid-State …, 2016 - ieeexplore.ieee.org
We present a novel frequency tracking method that exploits the dynamics of injection locking
in a quadrature ring oscillator to increase the effective locking range from 5%(7-7.4 GHz) to …
in a quadrature ring oscillator to increase the effective locking range from 5%(7-7.4 GHz) to …
22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS
M Raj, S Saeedi, A Emami - 2015 IEEE International Solid …, 2015 - ieeexplore.ieee.org
Modern SoC systems impose stringent requirements on on-chip clock generation and
distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the …
distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the …
A 12 Gb/s 0.9 mW/Gb/s wide-bandwidth injection-type CDR in 28 nm CMOS with reference-free frequency capture
T Masuda, R Shinoda, J Chatwin… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A wide band, low power, injection-locked oscillator (ILO)-type clock and data recovery
(CDR) with high jitter tolerance is implemented in 28 nm CMOS. A robust phase and …
(CDR) with high jitter tolerance is implemented in 28 nm CMOS. A robust phase and …
A 1.62 Gb/s–2.7 Gb/s referenceless transceiver for DisplayPort v1. 1a with weighted phase and frequency detection
This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency
detection of random signals. A single loop referenceless CDR is also proposed to overcome …
detection of random signals. A single loop referenceless CDR is also proposed to overcome …
Low-latency, frequency-agile clock multiplier
In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
Integrated circuit comprising fractional clock multiplication circuitry
Circuitry capable of performing fractional clock multiplica tion by using an injection-locked
oscillator is described. Some embodiments described herein perform fractional clock …
oscillator is described. Some embodiments described herein perform fractional clock …