Escalating system-on-chip design complexity is pushing the design community to raise the
level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of …

To extend the exponential performance scaling of future chip multiprocessors, improving
energy efficiency has become a first-class priority. Single-chip heterogeneous computing …

This paper presents an architecture framework to easily design hardware accelerators that
can effectively tolerate long and variable memory latency using prefetching and …

We describe new multi-ported cache designs suitable for use in FPGA-based
processor/parallel-accelerator systems, and evaluate their impact on application …

High-level-synthesis (HLS) tools generate accelerators from software programs to ease the
task of building hardware. Unfortunately, current HLS tools have limited support for …

Chip designers have shown increasing interest in integrating specialized fixed-function
coprocessors into multicore designs to improve energy efficiency. Recent work in academia …

Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA
accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor …

Emerging integrated CPU+ FPGA hybrid platforms, such as the Extensible Processing
Platform architecture from **linx [1], offer unprecedented opportunity to achieving both …

Memory-intensive implementations often require access to an external, off-chip memory
which can substantially slow down an FPGA accelerator due to memory bandwidth …

Complex “fat operators” are important contributors to the efficiency of specialized hardware.
This paper introduces two new techniques for constructing efficient fat operators featuring up …