FinFET cell architecture with power traces

J Kawa, V Moroz, DD Sherlekar - US Patent 9,691,764, 2017 - Google Patents
6,789,232 B1 9/2004 Iyer et al. 6,890,064 B2 5/2005 Torgerson et al. 7,737,501 B2 6, 2010
Zhu et al. 7,862.962 B2 1/2011 Shieh et al. 7,994,020 B2 8, 2011 Lin et al. 8,120,086 B2 …

High-speed low-leakage-power standard cell library

P Penzes, LIN Alvin, VJ Rakshani - US Patent 8,079,008, 2011 - Google Patents
Wireless devices such as phones and personal digital assis tants (PDAs) have become
essential business and personal tools. Users are requiring more and more functionality to be …

Manufacturing aware design and design aware manufacturing of an integrated circuit

A Fujimura, LK Scheffer - US Patent 8,020,135, 2011 - Google Patents
Some embodiments of the invention provide a process for designing and manufacturing an
integrated circuit (“IC). The process selects a wiring configuration and an illumina tion …

Aware manufacturing of integrated circuits

LK Scheffer, A Fujimura - US Patent 8,713,484, 2014 - Google Patents
Some embodiments of the invention provide a manufacturing aware process for designing
an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that …

System level simulation models for hardware modules

P Molson, T San, JR Fox - US Patent 7,509,246, 2009 - Google Patents
Generally, this invention pertains to methods of generating system level representations for
hardware modules. A “hard ware module'is any hardware functional block such as a …

Aware manufacturing of an integrated circuit

A Fujimura, LK Scheffer - US Patent 8,302,061, 2012 - Google Patents
6.829, 753 B2 12/2004 Lee et al. 2006/009014.6 A1 4/2006 LeBritton et al. 6.855. 486 B1
2/2005 Finders et al. 2006/0177747 A1 8, 2006 Misaka 687,338 B2 32005 Yamauchi …

Large cluster persistence during placement optimization of integrated circuit designs

MC Kim, S Ramji, PG Villarrubia… - US Patent …, 2016 - Google Patents
The disclosed herein relates to method for persistence during placement optimization of an
integrated circuit design. The method comprises performing cluster operation by grou** of …

Portable high capacity digital data storage device

SG Frost-Ruebling, JB Martin… - US Patent App. 11 …, 2007 - Google Patents
The present invention provides a portable data storage device compatible with both
standard and high definition digital video cameras. The device includes at least one SDI …

Nonlinear receiver model for gate-level delay calculation

HJ Levy - US Patent 7,299,445, 2007 - Google Patents
(58) Field of Classification Search.................. 716/17, a given receiver modeling situation
(signal type and oper ating conditions). The receiver model can then use different …

FinFET cell architecture with insulator structure

J Kawa, V Moroz, DD Sherlekar - US Patent 10,990,722, 2021 - Google Patents
US10990722B2 - FinFET cell architecture with insulator structure - Google Patents
US10990722B2 - FinFET cell architecture with insulator structure - Google Patents FinFET cell …