Network monitoring in software-defined networking: A review

PW Tsai, CW Tsai, CW Hsu, CS Yang - IEEE Systems Journal, 2018 - ieeexplore.ieee.org
Monitoring is an important concept in network management as it helps network operators to
determine the behavior of a network and the status of its components. Traffic engineering …

A survey of computer architecture simulation techniques and tools

A Akram, L Sawalha - Ieee Access, 2019 - ieeexplore.ieee.org
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …

[PDF][PDF] CACTI 6.0: A tool to model large caches

N Muralimanohar, R Balasubramonian, NP Jouppi - HP laboratories, 2009 - gitea.auro.re
Future processors will likely have large on-chip caches with a possibility of dedicating an
entire die for on-chip storage in a 3D stacked design. With the ever growing disparity …

[KNJIGA][B] Memory systems: cache, DRAM, disk

B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

Darwin: A genomics co-processor provides up to 15,000 x acceleration on long read assembly

Y Turakhia, G Bejerano, WJ Dally - ACM SIGPLAN Notices, 2018 - dl.acm.org
Genomics is transforming medicine and our understanding of life in fundamental ways.
Genomics data, however, is far outpacing Moore» s Law. Third-generation sequencing …

New cache designs for thwarting software cache-based side channel attacks

Z Wang, RB Lee - Proceedings of the 34th annual international …, 2007 - dl.acm.org
Software cache-based side channel attacks are a serious new class of threats for computers.
Unlike physical side channel attacks that mostly target embedded cryptographic devices …

Back to the future: Leveraging Belady's algorithm for improved cache replacement

A Jain, C Lin - ACM SIGARCH Computer Architecture News, 2016 - dl.acm.org
Belady's algorithm is optimal but infeasible because it requires knowledge of the future. This
paper explains how a cache replacement algorithm can nonetheless learn from Belady's …

Secure program execution via dynamic information flow tracking

GE Suh, JW Lee, D Zhang, S Devadas - ACM Sigplan Notices, 2004 - dl.acm.org
We present a simple architectural mechanism called dynamic information flow tracking that
can significantly improve the security of computing systems with negligible performance …

Temperature-aware microarchitecture

K Skadron, MR Stan, W Huang, S Velusamy… - ACM SIGARCH …, 2003 - dl.acm.org
With power density and hence cooling costs rising exponentially, processor packaging can
no longer be designed for the worst case, and there is an urgent need for runtime processor …

System level analysis of fast, per-core DVFS using on-chip switching regulators

W Kim, MS Gupta, GY Wei… - 2008 IEEE 14th …, 2008 - ieeexplore.ieee.org
Portable, embedded systems place ever-increasing demands on high-performance, low-
power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well …