Process, voltage, and temperature (PVT) variations in chip fabrication or operation pose a
significant challenge to the robustness of analog integrated circuits. Existing design …

This article introduces a compact NMOS-only voltage reference that is able to operate down
to a 0.25-V supply voltage and 5.4-pW power consumption. This allows reliable generation …

This article presents a nanowatt CMOS voltage reference using self-biased and capacitively
coupled schemes for improving the power supply rejection ratio (PSRR) and settling time …

This paper presents a high-precision bandgap voltage reference (BGR) with high-order
temperature compensation. The compensation signal is generated by using both strong …

This paper presents a curvature-compensated sub-1V voltage reference (VR) and a shared-
resistive nanoampere current reference (CR) in a 130nm CMOS process. The CR is used to …

In this paper, we propose an ultra-low power compact 3-transistor voltage reference capable
of operating at ultra-low supply voltages. The proposed circuit is based on the self-cascode …

This brief presents an NMOS-only voltage reference with small process variations for ultra-
low-power applications. All MOSFETs work in the subthreshold region and are biased by the …

This brief presents a picowatt PVT-insensitive CMOS voltage reference with ultra-low supply
voltage. The core circuit of the proposed reference consists of three subthreshold-biased …

A pico-watt, multi-output voltage reference for wireless sensor nodes has been proposed
and simulated in a 0.18-μ m CMOS process in this paper. To increase energy and area …

This paper presents a self-biased subthreshold CMOS voltage reference for low-power and
low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a …