A survey of computer architecture simulation techniques and tools

A Akram, L Sawalha - Ieee Access, 2019 - ieeexplore.ieee.org
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …

An evaluation of high-level mechanistic core models

TE Carlson, W Heirman, S Eyerman, I Hur… - ACM Transactions on …, 2014 - dl.acm.org
Large core counts and complex cache hierarchies are increasing the burden placed on
commonly used simulation and modeling techniques. Although analytical models provide …

The M5 simulator: Modeling networked systems

NL Binkert, RG Dreslinski, LR Hsu, KT Lim… - Ieee …, 2006 - ieeexplore.ieee.org
Developed specifically to enable research in TCP/IP networking, the M5 simulator provides
features necessary for simulating networked hosts, including full-system capability, a …

Review and evaluation of commonly-implemented background subtraction algorithms

Y Benezeth, PM Jodoin, B Emile… - 2008 19th …, 2008 - ieeexplore.ieee.org
Locating moving objects in a video sequence is the first step of many computer vision
applications. Among the various motion-detection techniques, background subtraction …

AVIO: detecting atomicity violations via access interleaving invariants

S Lu, J Tucek, F Qin, Y Zhou - ACM SIGOPS Operating Systems Review, 2006 - dl.acm.org
Concurrency bugs are among the most difficult to test and diagnose of all software bugs. The
multicore technology trend worsens this problem. Most previous concurrency bug detection …

Spatial memory streaming

S Somogyi, TF Wenisch, A Ailamaki, B Falsafi… - ACM SIGARCH …, 2006 - dl.acm.org
Prior research indicates that there is much spatial variation in applications' memory access
patterns. Modern memory systems, however, use small fixed-size cache blocks and as such …

SimFlex: statistical sampling of computer system simulation

TF Wenisch, RE Wunderlich, M Ferdman… - IEEE Micro, 2006 - ieeexplore.ieee.org
Timing-accurate full-system multiprocessor simulations can take years because of
architecture and application complexity. Statistical sampling makes simulation-based …

Multi-bit error tolerant caches using two-dimensional error coding

J Kim, N Hardavellas, K Mai, B Falsafi… - 40th Annual IEEE/ACM …, 2007 - ieeexplore.ieee.org
In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make
embedded memories increasingly vulnerable to reliability and yield problems. As scaling …

Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications

I Hwang, J Lee, H Kang, G Lee, H Kim - Simulation Modelling Practice and …, 2024 - Elsevier
In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …

A tagless coherence directory

J Zebchuk, V Srinivasan, MK Qureshi… - Proceedings of the 42nd …, 2009 - dl.acm.org
A key challenge in architecting a CMP with many cores is maintaining cache coherence in
an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop …