Recent research and emerging challenges in physical design for manufacturability/reliability
CW Lin, MC Tsai, KY Lee, TC Chen… - 2007 Asia and South …, 2007 - ieeexplore.ieee.org
As IC process geometries scale down to the nanometer territory, the industry faces severe
challenges of manufacturing limitations. To guarantee yield and reliability, physical design …
challenges of manufacturing limitations. To guarantee yield and reliability, physical design …
[LIBRO][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
High-performance routing at the nanometer scale
In this paper, we describe significant improvements to core routing technologies and
outperform the best results from the International Symposium on Physical Design 2007 …
outperform the best results from the International Symposium on Physical Design 2007 …
BoxRouter: A new global router based on box expansion and progressive ILP
In this paper, we propose a new global router, BoxRouter, powered by the concept of box
expansion and progressive integer linear programming (ILP). BoxRouter first uses a simple …
expansion and progressive integer linear programming (ILP). BoxRouter first uses a simple …
BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router
In this paper, we present BoxRouter 2.0, a hybrid and robust global router with discussion on
its architecture and implementation. As high performance VLSI design becomes more …
its architecture and implementation. As high performance VLSI design becomes more …
Stable and efficient reduction of substrate model networks using congruence transforms
KJ Kerns, IL Wemple, AT Yang - Proceedings of IEEE …, 1995 - ieeexplore.ieee.org
Parasitic analog-digital noise coupling has been identified as a key issue facing designers
of mixed-signal integrated circuits. In particular signal cross talk through the common chip …
of mixed-signal integrated circuits. In particular signal cross talk through the common chip …
CMP fill synthesis: A survey of recent studies
Chemical–mechanical polishing (CMP) is the planarizing technique of choice to satisfy the
local and global planarity constraints imposed by advanced lithography methods. The …
local and global planarity constraints imposed by advanced lithography methods. The …
NCTU-GR: Efficient simulated evolution-based rerouting and congestion-relaxed layer assignment on 3-D global routing
The increasing complexity of interconnection designs has enhanced the importance of
research into global routing when seeking high-routability (low overflow) results or rapid …
research into global routing when seeking high-routability (low overflow) results or rapid …
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As
high-performance VLSI design becomes more interconnect-dominant, efficient congestion …
high-performance VLSI design becomes more interconnect-dominant, efficient congestion …
Global and detailed routing
HY Chen, YW Chang - Electronic Design Automation, 2009 - Elsevier
Publisher Summary This chapter focuses on routing, a process that determines the precise
paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the …
paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the …