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A simulation study of junctionless double-gate metal-oxide-semiconductor field-effect transistor with symmetrical side gates
This study simulated the structure of a Junctionless (JL) Double-Gate (DG) Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) with symmetrical Side Gates (SG) and …
Semiconductor Field Effect Transistor (MOSFET) with symmetrical Side Gates (SG) and …
A nanoscale junctionless FET to amend the electric field distribution using a β-Ga2O3 packet
This paper describes a junctionless double-gate FET at nanoscale dimensions that utilizes a
ß-Ga2O3 packet to improve and amend the electric field at the device's beginning and in the …
ß-Ga2O3 packet to improve and amend the electric field at the device's beginning and in the …
SOI-MESFET with a layer of metal in buried oxide and a layer of SiO2 in channel to improve RF and breakdown characteristics
A Naderi, KM Satari, F Heirani - Materials Science in Semiconductor …, 2018 - Elsevier
A novel silicon on insulator metal semiconductor field effect transistor (SOI MESFET)
structure is presented in this paper. The proposed structure includes a thin layer of nickel …
structure is presented in this paper. The proposed structure includes a thin layer of nickel …
DC and RF characteristics improvement in SOI-MESFETs by inserting additional SiO2 layers and symmetric Si wells
S Khanjar, A Naderi - Materials Science and Engineering: B, 2021 - Elsevier
This paper presents an efficient structure for silicon on insulator metal semiconductor FETs.
In this structure, by using two symmetrical SiO 2 pieces on both sides of the channel and …
In this structure, by using two symmetrical SiO 2 pieces on both sides of the channel and …
[HTML][HTML] Improved MRD 4H-SiC MESFET with high power added efficiency
S Zhu, H Jia, X Wang, Y Liang, Y Tong, T Li, Y Yang - Micromachines, 2019 - mdpi.com
An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor
field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed …
field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed …
Enhanced performance of SOI MESFETs by displacement of gate contact and applying double oxide packets
In this paper, a new efficient technique is used in silicon-on-insulator metal–semiconductor
field-effect transistors (SOI MESFETs) to simultaneously increase the breakdown voltage …
field-effect transistors (SOI MESFETs) to simultaneously increase the breakdown voltage …
Physical analysis on the DC and RF operations of a novel SOI-MESFET with protruded gate and dual wells
In this article, a novel SOI MESFET which can be suitable for high power applications is
proposed. In order to upgrade its electrical characteristics, a protruded gate and dual wells …
proposed. In order to upgrade its electrical characteristics, a protruded gate and dual wells …
High breakdown voltage and high driving current in a novel silicon-on-insulator MESFET with high-and low-resistance boxes in the drift region
A Naderi, H Mohammadi - The European Physical Journal Plus, 2018 - Springer
In this paper a novel silicon-on-insulator metal oxide field effect transistor (SOI-MESFET)
with high-and low-resistance boxes (HLRB) is proposed. This structure increases the current …
with high-and low-resistance boxes (HLRB) is proposed. This structure increases the current …
Introducing a buried pure silicon layer in SOI-MESFET transistor to increase the breakdown voltage by modifying carriers and electric field distribution
L Pu, L Yan, W Hanlei - Emergent Materials, 2023 - Springer
Abstracts Due to the desirable features of the silicon-on-insulator metal-semiconductor field-
effect transistor (SOI MESFET), there are convincing reasons for the massive use of these …
effect transistor (SOI MESFET), there are convincing reasons for the massive use of these …
Embedding Two P+ Pockets in the Buried Oxide of Nano Silicon on Insulator MOSFETs: Controlled Short Channel Effects and Electric Field
Z Aghaeipour, A Naderi - Silicon, 2020 - Springer
This paper proposes an efficient structure for nanoscale silicon on insulator (SOI) MOSFETs.
Two P+ pockets are considered in buried oxide, a pocket under source region and another …
Two P+ pockets are considered in buried oxide, a pocket under source region and another …