G06F7/48—Methods or arrangements for performing computations using exclusively
denominational number representation, eg using binary, ternary, decimal representation …

A high-speed multiplier adapted to VLSI with a regu larly arranged structure having a
reduced number of addition stages. There is provided a carry save adder circuit wherein a …

In accordance with the present invention, a multiplier circuit is provided which comprises a
multiplier core having a rectangular aspect ratio (that is, a multiplier circuit for multiplying …

The invention performs the multiplication and/or accumulation of digital numbers in either
two's complement of unsigned magnitude representation. A modified Booth algorithm …

In accordance with the present invention, a con volver is comprised of N-1 buffers for storing
N-1 rasters (scan lines) of pixel values for an n-by-n kernel. The necessary multiplications …

A complex arithmetic unit (CAU) for manipulating digital data representative of complex
numbers. The CAU receives control signals and digital data represen tative of the real and …

57 ABSTRACT A rounding circuit (10) for converting and rounding an Mbit output from an
adder array (12) into a N bit binary magnitude representation includes an incrementer (18) …

A binary multiplication cell circuit suitable for a MOS transistor integrated circuit. The cell
circuit has a NOR circuit for obtaining a partial product of one binary digit of a multiplicand …

The present invention includes a method and apparatus for arithmetic operations. The
algorithms employed in the digital circuits permit fast multiplication of two n-bit X n-bit …

US4800517A - Word-sliced signal processor - Google Patents US4800517A - Word-sliced
signal processor - Google Patents Word-sliced signal processor Download PDF Info Publication …