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A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
This work presents a low-spur and low-jitter fractional-digital phase-locked loop (PLL). To
reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC) …
reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC) …
Linearized Analysis and Quantization Error Minimization for Mid-Rise TDCs: A Tutorial
The mid-rise time-to-digital converter (TDC), eg, a binary (bang-bang) phase detector and
other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked …
other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked …
A 265- W Fractional- Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65 …
This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …
[HTML][HTML] Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art
This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
A Fractional- Sampling PLL With a Merged Constant-Slope DTC and Sampling PD
This article presents a 3.3–4.5-GHz fractional-analog sampling phase-locked loop (SPLL). A
merged constant-slope digital-to-time converter and sampling phase detector (CSDTC-SPD) …
merged constant-slope digital-to-time converter and sampling phase detector (CSDTC-SPD) …
A charge-sharing locking technique with a general phase noise theory of injection locking
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of− 256 dB
An active-mixer-adopted sub-sampling phase-locked loop (AMASS-PLL) is presented that
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth
In this article, a mixed–signal, 32-kHz reference-based 2.4-GHz fractional-over-sampling
phase-locked loop (OSPLL) is proposed. Different from the conventional sampling PLL …
phase-locked loop (OSPLL) is proposed. Different from the conventional sampling PLL …