Synthesis and applications of III–V nanowires
E Barrigón, M Heurlin, Z Bi, B Monemar… - Chemical …, 2019 - ACS Publications
Low-dimensional semiconductor materials structures, where nanowires are needle-like one-
dimensional examples, have developed into one of the most intensely studied fields of …
dimensional examples, have developed into one of the most intensely studied fields of …
State of the art and future perspectives in advanced CMOS technology
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …
historical end point and we observe that the semiconductor industry is driving …
Challenges and limitations of CMOS scaling for FinFET and beyond architectures
A Razavieh, P Zeitzoff, EJ Nowak - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-
Line (MOL) device parameters, is systematically investigated. It is concluded that the …
Line (MOL) device parameters, is systematically investigated. It is concluded that the …
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman… - … on Electron Devices, 2017 - ieeexplore.ieee.org
In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from
intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and …
intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and …
Demonstration of germanium vertical gate-all-around field-effect transistors featured by self-aligned high-κ metal gates with record high performance
A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA)
field-effect transistor (FET)(Ge NW/NS pVSAFET) with self-aligned high-κ metal gates …
field-effect transistor (FET)(Ge NW/NS pVSAFET) with self-aligned high-κ metal gates …
Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures
Abstract Two-dimensional (2D) semiconductor-based vertical-transport field-effect
transistors (VTFETs)–in which the current flows perpendicularly to the substrate surface …
transistors (VTFETs)–in which the current flows perpendicularly to the substrate surface …
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
In-memory computing can be used to overcome the von Neumann bottleneck—the need to
shuffle data between separate memory and computational units—and help improve …
shuffle data between separate memory and computational units—and help improve …
Vertical tunnel FET: Design optimization with triple metal-gate layers
The effect of a triple metal-gate (TMG) on the performance and on the ambipolar current in a
TMG vertical tunnel field-effect transistor with triple metal-gate (TMG-TFET) is investigated …
TMG vertical tunnel field-effect transistor with triple metal-gate (TMG-TFET) is investigated …
Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation
X Yin, Y Zhang, H Zhu, GL Wang, JJ Li… - IEEE Electron …, 2019 - ieeexplore.ieee.org
A new type of vertical nanowire (NW)/nanosheet (NS) field-effect transistors (FETs), termed
vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work …
vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work …
Characteristics of stacked gate-all-around Si nanosheet MOSFETs with metal sidewall source/drain and their impacts on CMOS circuit properties
In this brief, we computationally examine electrical characteristics of stacked gate-all-around
Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) …
Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) …