A survey of research and practices of network-on-chip

T Bjerregaard, S Mahadevan - ACM Computing Surveys (CSUR), 2006 - dl.acm.org
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

Performance and accuracy of hardware-oriented native-, emulated-and mixed-precision solvers in FEM simulations

D Göddeke, R Strzodka, S Turek - International Journal of Parallel …, 2007 - Taylor & Francis
In this survey paper, we compare native double precision solvers with emulated-and mixed-
precision solvers of linear systems of equations as they typically arise in finite element …

Plasticine: A reconfigurable architecture for parallel paterns

R Prabhakar, Y Zhang, D Koeplinger… - ACM SIGARCH …, 2017 - dl.acm.org
Reconfigurable architectures have gained popularity in recent years as they allow the
design of energy-efficient accelerators. Fine-grain fabrics (eg FPGAs) have traditionally …

FPGA architecture: Survey and challenges

I Kuon, R Tessier, J Rose - Foundations and Trends® in …, 2008 - nowpublishers.com
Abstract Field-Programmable Gate Arrays (FPGAs) have become one of the key digital
circuit implementation media over the last decade. A crucial part of their creation lies in their …

A survey on coarse-grained reconfigurable architectures from a performance perspective

A Podobas, K Sano, S Matsuoka - IEEE Access, 2020 - ieeexplore.ieee.org
With the end of both Dennard's scaling and Moore's law, computer users and researchers
are aggressively exploring alternative forms of computing in order to continue the …

Brook for GPUs: stream computing on graphics hardware

I Buck, T Foley, D Horn, J Sugerman… - ACM transactions on …, 2004 - dl.acm.org
In this paper, we present Brook for GPUs, a system for general-purpose computation on
programmable graphics hardware. Brook extends C to include simple data-parallel …

Stream-dataflow acceleration

T Nowatzki, V Gangadhar, N Ardalani… - Proceedings of the 44th …, 2017 - dl.acm.org
Demand for low-power data processing hardware continues to rise inexorably. Existing
programmable and" general purpose" solutions (eg. SIMD, GPGPUs) are insufficient, as …

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

AB Kahng, B Li, LS Peh… - 2009 Design, Automation & …, 2009 - ieeexplore.ieee.org
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the
scalable fabric for interconnecting the cores. With power now the first-order design …

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

A 5-GHz mesh interconnect for a teraflops processor

Y Hoskote, S Vangal, A Singh, N Borkar, S Borkar - IEEE micro, 2007 - ieeexplore.ieee.org
A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores
delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on …