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Smartphone security and privacy: a survey on APTs, sensor-based attacks, side-channel attacks, google play attacks, and defenses
There is an exponential rise in the use of smartphones in government and private institutions
due to business dependencies such as communication, virtual meetings, and access to …
due to business dependencies such as communication, virtual meetings, and access to …
Armed cats: Formal concurrency modelling at arm
J Alglave, W Deacon, R Grisenthwaite… - ACM Transactions on …, 2021 - dl.acm.org
We report on the process for formal concurrency modelling at Arm. An initial formal
consistency model of the Arm achitecture, written in the cat language, was published and …
consistency model of the Arm achitecture, written in the cat language, was published and …
Compass: strong and compositional library specifications in relaxed memory separation logic
Several functional correctness criteria have been proposed for relaxed-memory consistency
libraries, but most lack support for modular client reasoning. Mével and Jourdan recently …
libraries, but most lack support for modular client reasoning. Mével and Jourdan recently …
Revam** hardware persistency models: view-based and axiomatic persistency models for Intel-x86 and Armv8
Non-volatile memory (NVM) is a cutting-edge storage technology that promises the
performance of DRAM with the durability of SSD. Recent work has proposed several …
performance of DRAM with the durability of SSD. Recent work has proposed several …
Formal verification of a multiprocessor hypervisor on arm relaxed memory hardware
Concurrent systems software is widely-used, complex, and error-prone, posing a significant
security risk. We introduce VRM, a new framework that makes it possible for the first time to …
security risk. We introduce VRM, a new framework that makes it possible for the first time to …
An axiomatic basis for computer programming on the relaxed arm-a architecture: The axsl logic
Very relaxed concurrency memory models, like those of the Arm-A, RISC-V, and IBM Power
hardware architectures, underpin much of computing but break a fundamental intuition …
hardware architectures, underpin much of computing but break a fundamental intuition …
Pomsets with preconditions: a simple model of relaxed memory
Relaxed memory models must simultaneously achieve efficient implementability and thread-
compositional reasoning. Is that why they have become so complicated? We argue that the …
compositional reasoning. Is that why they have become so complicated? We argue that the …
Putting weak memory in order via a promising intermediate representation
We investigate the problem of develo** an" in-order" shared-memory concurrency model
for languages like C and C++, which executes instructions following their program order …
for languages like C and C++, which executes instructions following their program order …
[PDF][PDF] Relaxed virtual memory in Armv8-A
B Simner, A Armstrong… - European …, 2022 - library.oapen.org
Virtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-
memory concurrency semantics has not previously been investigated in detail. The …
memory concurrency semantics has not previously been investigated in detail. The …
HMC: Model checking for hardware memory models
Stateless Model Checking (SMC) is an effective technique for verifying safety properties of a
concurrent program by systematically exploring all of its executions. While SMC has been …
concurrent program by systematically exploring all of its executions. While SMC has been …