Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems

W Wang, P Mishra, S Ranka - Proceedings of the 48th Design …, 2011 - dl.acm.org
Multicore architectures, especially chip multi-processors, have been widely acknowledged
as a successful design paradigm. Existing approaches primarily target application-driven …

A fully static true-single-phase-clocked dual-edge-triggered flip-flop for near-threshold voltage operation in IoT applications

Y Lee, G Shin, Y Lee - IEEE Access, 2020 - ieeexplore.ieee.org
A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is
proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET …

Reuse of off-the-shelf components in C2-style architectures

N Medvidovic, P Oreizy, RN Taylor - Proceedings of the 19th …, 1997 - dl.acm.org
Reuse of large-grain software components offers the potential for significant savings in
application development cost and time. Successful comuonent reuse and substitutability …

Integrated power management for battery-indifferent systems with ultra-wide adaptation down to nW

L Lin, S Jain, M Alioto - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This article presents a power management unit (PMU) enabling ultra-wide power-
performance tradeoff well beyond voltage scaling, and adaptation to the sensed …

Hopscotch: A hardware-software co-design for efficient cache resizing on multi-core SoCs

Z Jiang, K Yang, N Fisher, N Guan… - … on Parallel and …, 2023 - ieeexplore.ieee.org
Following the trend of increasing autonomy in real-time systems, multi-core System-on-
Chips (SoCs) have enabled devices to better handle the large streams of data and intensive …

A multi-version approach to conflict resolution in distributed groupware systems

C Sun, D Chen - Proceedings 20th IEEE International …, 2000 - ieeexplore.ieee.org
Groupware systems are a special class of distributed computing systems which support
human-computer-human interaction. Real-time collaborative graphics editors allow a group …

Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy

A Asad, O Ozturk, M Fathy… - Microprocessors and …, 2017 - Elsevier
Management of a problem recently known as “dark silicon” is a new challenge in multicore
designs. Prior innovative studies have addressed the dark silicon problem in the fields of …

Efficient cache reconfiguration using machine learning in NoC-based many-core CMPs

S Charles, A Ahmed, UY Ogras, P Mishra - ACM Transactions on Design …, 2019 - dl.acm.org
Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy
consumption in many-core architectures. While early work on DCR has shown promising …

Dynamically adaptable pipeline for energy-efficient microarchitectures under wide voltage scaling

S Jain, L Lin, M Alioto - IEEE Journal of Solid-State Circuits, 2017 - ieeexplore.ieee.org
This paper introduces dynamically adaptable pipelines to enable microarchitecture-driven
voltage scaling, adapting the microarchitecture to the most energy-efficient configuration for …

Cache reconfiguration using machine learning for vulnerability-aware energy optimization

A Ahmed, Y Huang, P Mishra - ACM Transactions on Embedded …, 2019 - dl.acm.org
Dynamic cache reconfiguration has been widely explored for energy optimization and
performance improvement for single-core systems. Cache partitioning techniques are …