A survey on application map** strategies for network-on-chip design

PK Sahu, S Chattopadhyay - Journal of systems architecture, 2013 - Elsevier
Application map** is one of the most important dimensions in Network-on-Chip (NoC)
research. It maps the cores of the application to the routers of the NoC topology, affecting the …

Noxim: An open, extensible and cycle-accurate network on chip simulator

V Catania, A Mineo, S Monteleone… - 2015 IEEE 26th …, 2015 - ieeexplore.ieee.org
Emerging on-chip communication technologies like wireless Networks-on-Chip (WiNoCs)
have been proposed as candidate solutions for addressing the scalability limitations of …

Cycle-accurate network on chip simulation with noxim

V Catania, A Mineo, S Monteleone, M Palesi… - ACM Transactions on …, 2016 - dl.acm.org
The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC
(MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it …

A survey on fault-tolerant application map** techniques for network-on-chip

N Kadri, M Koudil - Journal of Systems Architecture, 2019 - Elsevier
Reliability is becoming a major concern in Networks-on-Chips (NoCs) design. Several
techniques have been proposed in the literature to deal with different types of faults at …

[PDF][PDF] Design and simulation of ring network-on-chip for different configured nodes

A Jain, RK Dwivedi, H Alshazly, A Kumar… - … , Materials & Continua, 2022 - researchgate.net
The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a
back-end problem. The physical substructure that transfers data on the chip and ensures the …

An analytical latency model for networks-on-chip

AE Kiasari, Z Lu, A Jantsch - IEEE Transactions on Very Large …, 2012 - ieeexplore.ieee.org
We propose an analytical model based on queueing theory for delay analysis in a wormhole-
switched network-on-chip (NoC). The proposed model takes as input an application …

[KÖNYV][B] Digital design of signal processing systems: a practical approach

SA Khan - 2011 - books.google.com
Digital Design of Signal Processing Systems discusses a spectrum of architectures and
methods for effective implementation of algorithms in hardware (HW). Encompassing all …

Evaluation of low power consumption network on chip routing architecture

TS Arulananth, M Baskar, US SM, R Thiagarajan… - Microprocessors and …, 2021 - Elsevier
Abstract Network on Chip (NoC) is growing technology whereby multiprocessor state
interconnect patterns are formed. NoC technology is adapted to support a variety of …

An abacus turn model for time/space-efficient reconfigurable routing

B Fu, Y Han, J Ma, H Li, X Li - Proceedings of the 38th annual …, 2011 - dl.acm.org
Applications' traffic tends to be bursty and the location of hot-spot nodes moves as time goes
by. This will significantly aggregate the blocking problem of wormhole-routed Network-on …

[PDF][PDF] Evolution equations for continuous-scale morphology.

RW Brockett, P Maragos - icassp, 1992 - cvsp.cs.ntua.gr
Multiscale signal analysis has recently emerged as a useful framework for many computer
vision and signal processing tasks. Morphological filters can be used to develop nonlinear …