A new chaos-based PRNG hardware architecture using the HUB fixed-point format

SS Da Silva, M Cardoso, L Nardo… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
Chaotic systems have been applied in many applications involving instrumentation and
measurements, such as in sensors and control systems, due to their pseudorandom …

Area-latency efficient floating point adder using interleaved alignment and normalization

S Pitchai, S Pitchai - Microprocessors and Microsystems, 2023 - Elsevier
The barrel shifter is an indispensable floating-point (FP) adder circuit. It performs the
alignment on the mantissa of the smallest FP number and also normalizes the added …

Compact MAX and MIN stochastic computing architectures

PP Sotiriadis, N Temenos - Integration, 2022 - Elsevier
In this work we present Stochastic Computing MAX and MIN architectures. Their operation
relies on an accumulator to store the signed-bit differences between their two stochastic …

Optimized Fixed Point MAC Unit for Neural Network on FPGA

F Kordi, P Fortier, A Miled - 2024 International Conference on …, 2024 - ieeexplore.ieee.org
In recent years, the demand for efficient deep learning models has accelerated the
exploration of low-precision data representations that maintain competitive accuracy levels …

Exploring Temperature, Power, and Hardware Utilization in Half Adder Implementation on FPGA Platforms

G Singh, A Kaur - 2024 2nd International Conference on …, 2024 - ieeexplore.ieee.org
This study focused on energy efficiency, investigates the execution of an adder system on
several FPGA boards using Vivado **linx software. By employing thorough optimization …

A Simple Numerical Solution Framework for Ordinary Differential Equations Based on Reduced MIPS Instructions

Q Meng, X Jiang - 2022 IEEE 4th International Conference on …, 2022 - ieeexplore.ieee.org
Recently, numerical solutions for Ordinary Differential Equations (ODEs) based on fourth-
order Runge-Kutta method and fast Euler method are becoming more popular, however …