Identification of key nodes in aircraft state network based on complex network theory
W Zekun, W **angxi, W Minggong - IEEE Access, 2019 - ieeexplore.ieee.org
With the development of aviation, the air traffic density in the terminal area is high and the
traffic situation is relatively complex, which brings challenges to the flight deployment. In …
traffic situation is relatively complex, which brings challenges to the flight deployment. In …
3D multilayer mesh NoC communication and FPGA synthesis
Network on chip (NoC) is the latest approach in which multiprocessors are integrated in a
single chip and FPGA implementation makes it scalable and reconfigurable. It is the feasible …
single chip and FPGA implementation makes it scalable and reconfigurable. It is the feasible …
Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips
3-Dimensional Networks-on-Chips (3D NoCs) are proposed as the next generation
interconnect infrastructure for multi/many core embedded systems due to the high …
interconnect infrastructure for multi/many core embedded systems due to the high …
[PDF][PDF] A study of optimization techniques for 3d networks-on-chip architectures for low power and high performance applications
MO Agyeman - International Journal of Computer Applications, 2015 - Citeseer
ABSTRACT Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing
interest to solve on-chip communication demands of future multi-core embedded systems …
interest to solve on-chip communication demands of future multi-core embedded systems …
NoCDepend: A flexible and scalable Dependability Technique for 3D Networks-on-Chip
In order to be able to handle an arbitrary amount of static communication segment faults in
NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this …
NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this …
A Framework for Scalable TSV Assignment and Selection in Three‐Dimensional Networks‐on‐Chips
3D integration can greatly benefit future many‐cores by enabling low‐latency three‐
dimensional Network‐on‐Chip (3D‐NoC) topologies. However, due to high cost, low yield …
dimensional Network‐on‐Chip (3D‐NoC) topologies. However, due to high cost, low yield …
An overview of multicast routing algorithms in network on chip
In this silicon era, the major issues in CMOS submicron technologies are characterized by
extended gate lengths which introduce delays, signal integrity and unsynchronized …
extended gate lengths which introduce delays, signal integrity and unsynchronized …
An adaptive feature selection method for microarray data analysis
J Cheng, J Greshock, L Shi, J Painter… - 2012 IEEE …, 2012 - ieeexplore.ieee.org
Feature selection is one of the most important research topics in high dimensional array data
analysis. We propose a two-way filtering based method that utilizes a pair of statistics …
analysis. We propose a two-way filtering based method that utilizes a pair of statistics …
Design, Parallel Simulation and Implementation of High-Performance Fault-Tolerant Network-on-Chip Architectures
MEA Charif - 2017 - theses.hal.science
Networks-on-Chip (NoCs) have proven to be a fast and scalable replacement for buses in
current and emerging many-core systems. They are today an actively researched topic and …
current and emerging many-core systems. They are today an actively researched topic and …
3D NoC 关键通信部件容错方法研究综述
欧阳一鸣， 孙成龙， 陈奇， 梁华国， 易茂祥， 黄**峰… - 电子学报, 2016 - ejournal.org.cn
三维片上网络通过硅通孔(Through Silicon Via, TSV) 将多层芯片进行堆叠, 具有集成密度大,
通信效率高等特点, 是片上多核系统的主流通信架构. 然而, 工艺偏差及物理缺陷所引发的错误和 …
通信效率高等特点, 是片上多核系统的主流通信架构. 然而, 工艺偏差及物理缺陷所引发的错误和 …