Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
On using lossless compression of debug data in embedded logic analysis
E Anis, N Nicolici - 2007 IEEE International Test Conference, 2007 - ieeexplore.ieee.org
The capacity of on-chip trace buffers employed for embedded logic analysis limits the
observation window of a debug experiment. To increase the debug observation window, we …
observation window of a debug experiment. To increase the debug observation window, we …
Low cost debug architecture using lossy compression for silicon debug
E Anis, N Nicolici - 2007 Design, Automation & Test in Europe …, 2007 - ieeexplore.ieee.org
The size of on-chip trace buffers used for at-speed silicon debug limits the observation
window in any debug session. Whenever the debug experiment can be repeated, we …
window in any debug session. Whenever the debug experiment can be repeated, we …
Visibility enhancement for silicon debug
YC Hsu, F Tsai, W Jong, YT Chang - Proceedings of the 43rd annual …, 2006 - dl.acm.org
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by
making internal signal values and other data observable. Most of these methodologies …
making internal signal values and other data observable. Most of these methodologies …
Resource-efficient programmable trigger units for post-silicon validation
HF Ko, N Nicolici - 2009 14th IEEE European Test Symposium, 2009 - ieeexplore.ieee.org
The decisions on when to acquire debug data during post-silicon validation are determined
by trigger events that are programmed into on-chip trigger units. In this paper, we investigate …
by trigger events that are programmed into on-chip trigger units. In this paper, we investigate …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Method for fabrication of a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …