Power-aware test: Challenges and solutions
S Ravi - 2007 IEEE International Test Conference, 2007 - ieeexplore.ieee.org
Power-aware test is increasingly becoming a major manufacturing test consideration due to
the problems of increased power dissipation in various test modes as well as test …
the problems of increased power dissipation in various test modes as well as test …
[BOOK][B] Design of 3D integrated circuits and systems
R Sharma - 2018 - books.google.com
Three-dimensional (3D) integration of microsystems and subsystems has become essential
to the future of semiconductor technology development. 3D integration requires a greater …
to the future of semiconductor technology development. 3D integration requires a greater …
Low Power Testing—What Can Commercial Design-for-Test Tools Provide?
X Lin - Journal of Low Power Electronics and Applications, 2011 - mdpi.com
Minimizing power consumption during functional operation and during manufacturing tests
has become one of the dominant requirements for the semiconductor designs in the past …
has become one of the dominant requirements for the semiconductor designs in the past …
Architecture for testing multi-voltage domain SOC
L Souef, C Eychenne, E Alie - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
In portable applications power consumption is a key parameter to commercial success.
Mobile phone standby time, talk time and MP3 player play time are key customer …
Mobile phone standby time, talk time and MP3 player play time are key customer …
Low power testing-What can commercial DFT tools provide?
X Lin - 2011 International Green Computing Conference and …, 2011 - ieeexplore.ieee.org
Minimizing power consumption during functional operation and during manufacturing test
has become one of the dominant requirements for the semiconductor designs in the past …
has become one of the dominant requirements for the semiconductor designs in the past …
Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies
R Swanson, A Wong, S Ethirajan… - 2014 19th IEEE …, 2014 - ieeexplore.ieee.org
A new industry-wide trend is the presence of multiple on-die power-supplies that are not
directly connected to external supplies. Examples are internally-regulated supplies and …
directly connected to external supplies. Examples are internally-regulated supplies and …
Built‐in self test design of power switch with clock‐gated charge/discharge transistor
It is becoming common to implement header (footer) power switches in low‐power system‐
on‐chip. However, the switches are not tested for manufacturing defects in most designs …
on‐chip. However, the switches are not tested for manufacturing defects in most designs …
Testing retention flip-flops in power-gated designs
HW Hsu, SH Kuo, WH Chang, SH Chen… - 2013 IEEE 31st VLSI …, 2013 - ieeexplore.ieee.org
This paper focuses on tackling two problems on testing retention flip-flops in power-gated
designs. The first one is how to reduce the virtual-V DD discharge time after entering the …
designs. The first one is how to reduce the virtual-V DD discharge time after entering the …
[BOOK][B] Power-efficient tightly-coupled processor arrays for digital signal processing
D Kissler - 2012 - search.proquest.com
In this thesis, we focus on highly area-and power-efficient, massively parallel, tightly-coupled
embedded hardware architectures called Weakly Programmable Processor Arrays (WPPA) …
embedded hardware architectures called Weakly Programmable Processor Arrays (WPPA) …
BIST design of power switch
It is becoming common to implement power switches in low power system-on-chip (SoC).
However, the power switches are not tested for manufactory defects in most designs …
However, the power switches are not tested for manufactory defects in most designs …