[LIVRE][B] Handbook of data structures and applications

DP Mehta, S Sahni - 2004 - taylorfrancis.com
Although there are many advanced and specialized texts and handbooks on algorithms,
until now there was no book that focused exclusively on the wide variety of data structures …

Consistency constraints for map** dataflow graphs to hybrid dataflow/von neumann architectures

K Schneider, A Bhagyanath - ACM Transactions on Embedded …, 2023 - dl.acm.org
Dataflow process networks (DPNs) provide a convenient model of computation that is often
used to model system behavior in model-based designs. With fixed sets of nodes, they are …

Queue machines: hardware compilation in hardware

H Schmit, B Levine, B Ylvisaker - Proceedings. 10th Annual …, 2002 - ieeexplore.ieee.org
In this paper we hypothesize that reconfigurable computing is not more widely used
because of the logistical difficulties caused by the close coupling of applications and …

Toward a theory of planarity: Hanani-Tutte and planarity variants

M Schaefer - International Symposium on Graph Drawing, 2012 - Springer
Abstract We study Hanani-Tutte style theorems for various notions of planarity, including
partially embedded planarity, and simultaneous planarity. This approach brings together the …

Detecting weakly simple polygons

HC Chang, J Erickson, C Xu - Proceedings of the twenty-sixth annual ACM …, 2014 - SIAM
A closed curve in the plane is weakly simple if it is the limit (in the Fréchet metric) of a
sequence of simple closed curves. We describe an algorithm to determine whether a closed …

Allocation and scheduling of dataflow graphs on hybrid dataflow/von Neumann architectures

A Bhagyanath, N Kercher, K Schneider - Proceedings of the 21st ACM …, 2023 - dl.acm.org
Hybrid dataflow/von Neumann processors expose their processing units and datapaths to
the compiler to exploit the instruction-level parallelism of sequential programs. Generating …

Code generation criteria for buffered exposed datapath architectures from dataflow graphs

K Schneider, A Bhagyanath, J Roob - Proceedings of the 23rd ACM …, 2022 - dl.acm.org
Many novel processor architectures expose their processing units (PUs) and internal
datapaths to the compiler. To avoid an unnecessary synchronization of PUs, the datapaths …

Partial and constrained level planarity

G Brückner, I Rutter - Proceedings of the Twenty-Eighth Annual ACM-SIAM …, 2017 - SIAM
Abstract Let G=(V, E) be a directed graph and ℓ: V→[k]:={1,…, k} a level assignment such
that ℓ (u)< ℓ (v) for all directed edges (u, v)∊ E. A level planar drawing of G is a drawing of G …

Hanani–Tutte, monotone drawings, and level-planarity

R Fulek, MJ Pelsmajer, M Schaefer… - Thirty essays on …, 2013 - Springer
A drawing of a graph is x-monotone if every edge intersects every vertical line at most once
and every vertical line contains at most one vertex. Pach and Tóth showed that if a graph …

Level planar embedding in linear time

M Jünger, S Leipert - Graph Drawing: 7th International Symposium, GD'99 …, 1999 - Springer
In a level directed acyclic graph G=(V; E) the vertex set V is partitioned into k≤| V| levels V 1;
V 2... V k such that for each edge (u, v)∈ E with u∈ V i and v∈; V j we have i< j. The level …