Techniques described herein generally include methods and systems related to circuit
switching in a network-on-chip. According to embodiments of the disclosure, a network-on …

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture
for solid state memory struc tures, both volatile and non-volatile, which provide for the …

References Cited A packet-switched reservation request to be associated with a first data
stream is received. A communication mode is selected. The communication mode is to be …

The number of components on a chip is rapidly growing due to increasing levels of
integration, system complexity and shrinking transistor geometry. Complex System-on Chips …

Methods and apparatus of delegating instructions or data from a CU to an NOC node in a
network on chip (NOC) is disclosed. The NOC node executes the delegated instruc tions or …

In one embodiments, a system comprises: a plurality of scan test chains configured to
perform test operations at a first clock speed; a central test controller for controlling testing by …

G06F11/2205—Detection or location of defective computer hardware by testing during
standby operation or during idle time, eg start-up testing using arrangements specific to the …

BACKGROUND Networks-on-Chip (NoCs), for on-die communication between cores, are
important in enabling Scalable perfor mance as the number of cores and intellectual …

In one embodiment, a test system comprises: a plurality of test partitions and a centralized
controller configured to coordinate testing between the plurality of test partitions. At least one …

Embodiments described herein generally relate to the use of three-dimensional solid state
memory structures, both vola tile and non-volatile, utilizing a Network-on-Chip routing …