Suppression of current quantization effects for precise current control of SPMSM using dithering techniques and Kalman filter
High-precision current control is demanded for many mechatronic systems to improve the
static and dynamic performances. However, current measurement error inherent in the …
static and dynamic performances. However, current measurement error inherent in the …
A low complexity-high throughput QC-LDPC encoder
This paper introduces hardware architectures for encoding Quasi-Cyclic Low-Density Parity
Check (QC-LDPC) codes. The proposed encoders are based on appropriate factorization …
Check (QC-LDPC) codes. The proposed encoders are based on appropriate factorization …
Hardware-Efficient Architecture for Multiple Quantized Gaussian Noise Generation
K Choi, IC Park - IEEE Transactions on Circuits and Systems I …, 2025 - ieeexplore.ieee.org
This paper presents two novel architectures to generate a number of quantized Gaussian
noises. The first architecture exploits inversion through uniform segmentation, enabling a …
noises. The first architecture exploits inversion through uniform segmentation, enabling a …
Software/hardware parallel long-period random number generation framework based on the well method
Y Li, P Chow, J Jiang, M Zhang… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
This paper presents a hardware architecture for efficient implementation of the well
equidistributed long-period linear (WELL) algorithm. Our design achieves a throughput of …
equidistributed long-period linear (WELL) algorithm. Our design achieves a throughput of …
Area-efficient approach for generating quantized gaussian noise
This paper presents an efficient method to generate quantized Gaussian noise. The
proposed method is derived based on the fact that any signal received at a digital system …
proposed method is derived based on the fact that any signal received at a digital system …
An FPGA-based prototy** method for verification, characterization and optimization of LDPC error correction systems
P Sakellariou, I Tsatsaragkos… - 2012 International …, 2012 - ieeexplore.ieee.org
This paper introduces a methodology for forward error correction (FEC) architectures
prototy**, oriented to system verification and characterization. A complete design flow is …
prototy**, oriented to system verification and characterization. A complete design flow is …
Digital pseudorandom uniform noise generators for ADC histogram test
JD Alves, G Evans - 2015 Conference on Design of Circuits and …, 2015 - ieeexplore.ieee.org
This paper presents the evaluation of two different digital pseudorandom uniform noise
generators (UNGs) applied to ADC histogram test. Two 32 bits pseudorandom uniform noise …
generators (UNGs) applied to ADC histogram test. Two 32 bits pseudorandom uniform noise …
Error floor compensation for LDPC codes using concatenated schemes
G Spourlis, I Tsatsaragkos, N Kanistras… - 2012 IEEE Workshop …, 2012 - ieeexplore.ieee.org
This paper quantitatively investigates the trade-offs in the compensation of error floor on
iterative decoders. The characterization of iterative decoding systems prone to error floor at …
iterative decoders. The characterization of iterative decoding systems prone to error floor at …
A complete system to generate electrical noise with arbitrary power spectral density
Reliability and performance of electronic devices are significantly dependent on their noise
rejection capability that is usually investigated since their early production stage as well as …
rejection capability that is usually investigated since their early production stage as well as …
Multiple LDPC decoder of very low bit-error rate
I Tsatsaragkos, N Kanistras… - 2011 17th International …, 2011 - ieeexplore.ieee.org
The error correcting capability of LDPC based systems at low noise levels is often
dominated by the so-called error floor, a region in the BER vs. noise level plot, where BER …
dominated by the so-called error floor, a region in the BER vs. noise level plot, where BER …