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Improving performance and energy consumption in embedded systems via binary acceleration: A survey
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum
operating clock frequencies of processors. To mitigate this issue, computing shifted to multi …
operating clock frequencies of processors. To mitigate this issue, computing shifted to multi …
Modern architectures for embedded reconfigurable systems—a survey
Reconfigurable systems, exploiting a mixture of the traditional CPU-centric instruction-
stream-based processing with the decentralized parallel application-specific data …
stream-based processing with the decentralized parallel application-specific data …
Transparent trace-based binary acceleration for reconfigurable HW/SW systems
This paper presents a novel approach to accelerate program execution by map**
repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable …
repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable …
Transparent Runtime Migration of Loop‐Based Traces of Processor Instructions to Reconfigurable Processing Units
The ability to map instructions running in a microprocessor to a reconfigurable processing
unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and …
unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and …
From instruction traces to specialized reconfigurable arrays
This paper presents an offline tool-chain which automatically extracts loops (Mega blocks)
from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit …
from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit …
Compression of computed radiographic images using linear prediction on wavelet coefficients
Computed radiographic images are usually large in size. So for storage and transmission
the image should be compressed. This paper proposes a method in which image …
the image should be compressed. This paper proposes a method in which image …
Generation of Reconfigurable Circuits from Machine Code
NMC Paulino - 2011 - search.proquest.com
This work presents a system for automated generation of a hardware description that
implements a dedicated accelerator for a given program. The accelerator is run-time …
implements a dedicated accelerator for a given program. The accelerator is run-time …
Generation of Custom Run-time Reconfigurable Hardware for Transparent Binary Acceleration
NMC Paulino - 2016 - search.proquest.com
With the increase of application complexity and amount of data, the required computational
power increases in tandem. Technology improvements have allowed for the increase in …
power increases in tandem. Technology improvements have allowed for the increase in …
Interactive Tool for Specifying Dedicated Hardware Accelerators
JPP Rebocho - 2015 - search.proquest.com
O presente relatório tem como objetivo documentar todo o trabalho realizado durante
aunidade curricular: Dissertação de Mestrado Integrado em Engenharia Electrotécnica e …
aunidade curricular: Dissertação de Mestrado Integrado em Engenharia Electrotécnica e …
[PDF][PDF] Research Article Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Recon gura le Processing nits
J Bispo, N Paulino, JMP Cardoso, JC Ferreira - 2013 - academia.edu
Research Article Transparent Runtime Migration of Loop-Based Traces of Processor
Instructions to Recon gura le Processing Page 1 Hindawi Publishing Corporation …
Instructions to Recon gura le Processing Page 1 Hindawi Publishing Corporation …