A survey of research and practices of network-on-chip

T Bjerregaard, S Mahadevan - ACM Computing Surveys (CSUR), 2006 - dl.acm.org
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

A survey on application map** strategies for network-on-chip design

PK Sahu, S Chattopadhyay - Journal of systems architecture, 2013 - Elsevier
Application map** is one of the most important dimensions in Network-on-Chip (NoC)
research. It maps the cores of the application to the routers of the NoC topology, affecting the …

Energy-and performance-aware map** for regular NoC architectures

J Hu, R Marculescu - … Transactions on computer-aided design of …, 2005 - ieeexplore.ieee.org
In this paper, we present an algorithm which automatically maps a given set of intellectual
property onto a generic regular network-on-chip (NoC) architecture and constructs a …

Toward energy-efficient cloud computing: a survey of dynamic power management and heuristics-based optimization techniques

N Khattar, J Sidhu, J Singh - The Journal of Supercomputing, 2019 - Springer
Cloud computing is the most prominent computing paradigm in the present era of
information technology. However, data centers needed for hosting cloud services demand …

[PDF][PDF] Survey of network on chip (noc) architectures & contributions

A Agarwal, C Iskander, R Shankar - Journal of engineering …, 2009 - researchgate.net
Multiprocessor architectures and platforms have been introduced to extend the applicability
of Moore's law. They depend on concurrency and synchronization in both software and …

Key research problems in NoC design: a holistic perspective

UY Ogras, J Hu, R Marculescu - Proceedings of the 3rd IEEE/ACM/IFIP …, 2005 - dl.acm.org
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex
on-chip communication problems. The lack of an unified representation of applications and …

Linear-programming-based techniques for synthesis of network-on-chip architectures

K Srinivasan, KS Chatha… - IEEE Transactions on Very …, 2006 - ieeexplore.ieee.org
Application-specific system-on-chip (SoC) design offers the opportunity for incorporating
custom network-on-chip (NoC) architectures that are more suitable for a particular …

Temperature aware task scheduling in MPSoCs

AK Coskun, TS Rosing… - 2007 Design, Automation & …, 2007 - ieeexplore.ieee.org
In deep submicron circuits, elevation in temperatures has brought new challenges in
reliability, timing, performance, cooling costs and leakage power. Conventional thermal …

Dynamic thermal management in 3D multicore architectures

AK Coskun, JL Ayala, D Atienza… - … , Automation & Test …, 2009 - ieeexplore.ieee.org
Technology scaling has caused the feature sizes to shrink continuously, whereas
interconnects, unlike transistors, have not followed the same trend. Designing 3D stack …

On the decidability of metric temporal logic

J Ouaknine, J Worrell - 20th Annual IEEE Symposium on Logic …, 2005 - ieeexplore.ieee.org
Metric temporal logic (MTL) is a prominent specification formalism for real-time systems. In
this paper, we show that the satisfiability problem for MTL over finite timed words is …