Hardware trust and assurance through reverse engineering: A tutorial and outlook from image analysis and machine learning perspectives

UJ Botero, R Wilson, H Lu, MT Rahman… - ACM Journal on …, 2021 - dl.acm.org
In the context of hardware trust and assurance, reverse engineering has been often
considered as an illegal action. Generally speaking, reverse engineering aims to retrieve …

ASSURE: RTL locking against an untrusted foundry

C Pilato, AB Chowdhury, D Sciuto… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Semiconductor design companies are integrating proprietary intellectual property (IP) blocks
to build custom integrated circuits (ICs) and fabricate them in a third-party foundry …

Exploring eFPGA-based redaction for IP protection

J Bhandari, AKT Moosa, B Tan, C Pilato… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Recently, eFPGA-based redaction has been proposed as a promising solution for hiding
parts of a digital design from untrusted entities, where legitimate end-users can restore …

High-level approaches to hardware security: A tutorial

H Pearce, R Karri, B Tan - ACM Transactions on Embedded Computing …, 2023 - dl.acm.org
Designers use third-party intellectual property (IP) cores and outsource various steps in the
integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities …

SAIL: Analyzing structural artifacts of logic locking using machine learning

P Chakraborty, J Cruz, A Alaql… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Obfuscation or Logic locking (LL) is a technique for protecting hardware intellectual property
(IP) blocks against diverse threats, including IP theft, reverse engineering, and malicious …

AdaTest: Reinforcement learning and adaptive sampling for on-chip hardware Trojan detection

H Chen, X Zhang, K Huang, F Koushanfar - ACM Transactions on …, 2023 - dl.acm.org
This paper proposes AdaTest, a novel adaptive test pattern generation framework for
efficient and reliable Hardware Trojan (HT) detection. HT is a backdoor attack that tampers …

Benchmarking of soc-level hardware vulnerabilities: A complete walkthrough

S Tarek, H Al Shaikh, SR Rajendran… - 2023 IEEE Computer …, 2023 - ieeexplore.ieee.org
Due to the increasing complexity of modern system-on-chips (SoCs) and the diversity of the
attack surface, popular SoC verification approaches used in industry and academia for …

Not all fabrics are created equal: Exploring eFPGA parameters for IP redaction

J Bhandari, AKT Moosa, B Tan, C Pilato… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
Semiconductor design houses rely on third-party foundries to manufacture their integrated
circuits (ICs). While this trend allows them to tackle fabrication costs, it introduces security …

A survey and perspective on artificial intelligence for security-aware electronic design automation

D Koblah, R Acharya, D Capecci… - ACM Transactions on …, 2023 - dl.acm.org
Artificial intelligence (AI) and machine learning (ML) techniques have been increasingly
used in several fields to improve performance and the level of automation. In recent years …

ALICE: An automatic design flow for eFPGA redaction

CM Tomajoli, L Collini, J Bhandari, AKT Moosa… - Proceedings of the 59th …, 2022 - dl.acm.org
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design
houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the …