A cross-layer gate-level-to-application co-simulation for design space exploration of approximate circuits in HEVC video encoders
A cross-layer design space exploration (DSE) method based on a proposed co-simulation
technique is presented herein. The proposed method is demonstrated evaluating the …
technique is presented herein. The proposed method is demonstrated evaluating the …
Design and implementation of the Walsh–Hadamard transform on a ternary optical computer
W Zhehe, S Yunfu - Applied Optics, 2021 - opg.optica.org
Walsh–Hadamard is a commonly used mathematical transformation, a mathematical method
for spectrum analysis in the real number domain, which has been widely used in many fields …
for spectrum analysis in the real number domain, which has been widely used in many fields …
Affine Motion Estimation Hardware Implementation with 51.7%/67.5% Internal Bandwidth Reduction for Versatile Video Coding
S Chen, L Huang, Z Zan, Z Hao… - … on Circuits and …, 2024 - ieeexplore.ieee.org
Versatile Video Coding (VVC) employs Affine Motion Compensation (AMC) to process
scenes with high-order motion. To improve AMC efficiency, the Affine Motion Estimation …
scenes with high-order motion. To improve AMC efficiency, the Affine Motion Estimation …
SAD or SATD? how the distortion metric impacts a Fractional Motion Estimation VLSI architecture
Video coding systems have to deal with a number of tradeoffs. The decision of adopting a
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …
specific distortion metric in the Fractional Motion Estimation (FME) step, for instance …
Approximate SATD hardware accelerator using the 8× 8 Hadamard transform
MF Stigger, VHS Lima, LB Soares… - 2020 IEEE 11th Latin …, 2020 - ieeexplore.ieee.org
Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the
Hadamard Transform. It is used in current video encoders inside the refinement stage of …
Hadamard Transform. It is used in current video encoders inside the refinement stage of …
Variable Block Size Fractional Motion Estimation Hardware Architecture for VVC and HEVC Standards
The ever-increasing growth in digital video consumption motivates the research and
development of new video coding standards to improve coding efficiency. Among the …
development of new video coding standards to improve coding efficiency. Among the …
Tile adaptation for workload balancing of 3d-HEVC encoder in homogeneous multicore systems
This paper proposes a tile adaptation for workload balancing to speed up the 3D-High
Efficiency Video Coding (3D-HEVC) encoder. Experiments were done to evaluate the usage …
Efficiency Video Coding (3D-HEVC) encoder. Experiments were done to evaluate the usage …
The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures
Over the years, the use of adder compressors has been a promising alternative to reduce
power of dedicated hardware architectures. Adder compressors are able to perform several …
power of dedicated hardware architectures. Adder compressors are able to perform several …
Configurable approximate hardware accelerator to compute SATD and SAD metrics for low power all-intra high efficiency video coding
VHS Lima, MF Stigger, LB Soares… - 2021 34th SBC …, 2021 - ieeexplore.ieee.org
Connecting billions of network cameras to the cloud is a challenge that heavily taxes the
network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard …
network bandwidth for video transmissions. High Efficiency Video Coding (HEVC) standard …
High-level synthesis implementation of transform-exempted satd architectures for low-power video coding
T Partanen, A Lemmetti, P Sjövall… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
This paper presents the first known high-level synthesis (HLS) implementation for the Sum of
Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture …
Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture …