On the optimal design of triple modular redundancy logic for SRAM-based FPGAs

FL Kastensmidt, L Sterpone, L Carro… - … , Automation and Test …, 2005‏ - ieeexplore.ieee.org
Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based
FPGA. However, one of the main challenges in achieving 100% robustness in designs …

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

L Sterpone, M Violante - IEEE Transactions on Computers, 2006‏ - ieeexplore.ieee.org
The very high integration levels reached by VLSI technologies for SRAM-based field
programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced …

Analysis of the robustness of the TMR architecture in SRAM-based FPGAs

L Sterpone, M Violante - IEEE Transactions on Nuclear Science, 2005‏ - ieeexplore.ieee.org
Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very
sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus …

A review on SEU mitigation techniques for FPGA configuration memory

TS Nidhin, A Bhattacharyya, RP Behera… - IETE Technical …, 2018‏ - Taylor & Francis
Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …

A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-based FPGAs

L Sterpone, M Violante - IEEE Transactions on Nuclear Science, 2007‏ - ieeexplore.ieee.org
Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in
implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive …

Fast terrain classification using variable-length representation for autonomous navigation

A Angelova, L Matthies, D Helmick… - 2007 IEEE Conference …, 2007‏ - ieeexplore.ieee.org
We propose a method for learning using a set of feature representations which retrieve
different amounts of information at different costs. The goal is to create a more efficient …

An ALU protection methodology for soft processors on SRAM-based FPGAs

A Ramos, RG Toral, P Reviriego… - IEEE Transactions on …, 2019‏ - ieeexplore.ieee.org
The use of microprocessors in space missions implies that they should be protected against
the effects of cosmic radiation. Commonly this objective has been achieved by applying …

An efficient fault-tolerant instruction decoder for RISC-V based dual-core soft-processors

S Shukla, M Azam, KC Ray - IEEE Transactions on Circuits …, 2023‏ - ieeexplore.ieee.org
In the modern era, FPGA-based soft-core processors have gained much attention in space
applications due to their flexibility and ease of integration. In such applications, radiation can …

A new hardware/software platform and a new 1/E neutron source for soft error studies: Testing FPGAs at the ISIS facility

M Violante, L Sterpone, A Manuzzato… - … on Nuclear Science, 2007‏ - ieeexplore.ieee.org
We introduce a new hardware/software platform for testing SRAM-based FPGAs under
heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory …

Parity driven reconfigurable duplex system

J Borecký, M Kohlík, H Kubátová - Microprocessors and Microsystems, 2017‏ - Elsevier
This paper proposes a method improving the fault-coverage capabilities of (FPGA) designs.
Faults are mostly (SEUs) in the configuration memory of SRAM-based (FPGA) and they can …