A nonvolatile memory system, a nonvolatile memory controller and a method for reducing
latency of a memory controller are disclosed. Upon the occurrence of one or more of an …

Example methods, apparatus, and articles of manufacture to perform error detection and
correction are disclosed. A dis closed example method involves enabling a memory control …

An error check and scrub (ECS) mode enables a memory device to perform error checking
and correction (ECC) and count errors. An associated memory controller triggers the ECS …

Abstract A Solid State Drive (SSD) that includes a host connector receptacle for connecting
to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The …

An error check and scrub (ECS) mode enables a memory device to perform error checking
and correction (ECC) and count errors. An associated memory controller triggers the ECS …

An apparatus, method and system is described herein for efficiently balancing performance
and power between pro cessing elements based on measured workloads. If a work load of a …

A nonvolatile memory storage controller is provided for delivering log likelihood ratios
(LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC …

A system and method reading, accumulating and processing soft information for use in
LDPC decoding. In accordance with the present invention, an LDPC decoder includes …

A nonvolatile memory storage controller is provided for delivering log likelihood ratios
(LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC …

A nonvolatile memory controller includes memory storage configured to store a two-index
look-up table that includes a Log-Likelihood Ratio (LLR), hard-and-soft-decision bits …