The architectural implications of facebook's dnn-based personalized recommendation
The widespread application of deep learning has changed the landscape of computation in
data centers. In particular, personalized recommendation for content ranking is now largely …
data centers. In particular, personalized recommendation for content ranking is now largely …
DAWG: A defense against cache timing attacks in speculative execution processors
Software side channel attacks have become a serious concern with the recent rash of
attacks on speculative processor architectures. Most attacks that have been demonstrated …
attacks on speculative processor architectures. Most attacks that have been demonstrated …
Deeprecsys: A system for optimizing end-to-end at-scale neural recommendation inference
Neural personalized recommendation is the cornerstone of a wide collection of cloud
services and products, constituting significant compute demand of cloud infrastructure. Thus …
services and products, constituting significant compute demand of cloud infrastructure. Thus …
{HybCache}: Hybrid {Side-Channel-Resilient} caches for trusted execution environments
Modern multi-core processors share cache resources for maximum cache utilization and
performance gains. However, this leaves the cache vulnerable to side-channel attacks …
performance gains. However, this leaves the cache vulnerable to side-channel attacks …
Why on-chip cache coherence is here to stay
Why on-chip cache coherence is here to stay Page 1 78 CommuniCations oF the aCm | juLy 2012
| voL. 55 | no. 7 contributed articles shAred MeMorY is the dominant low-level communication …
| voL. 55 | no. 7 contributed articles shAred MeMorY is the dominant low-level communication …
Secure hierarchy-aware cache replacement policy (sharp) defending against cache-based side channel atacks
In cache-based side channel attacks, a spy that shares a cache with a victim probes cache
locations to extract information on the victim's access patterns. For example, in evict+ reload …
locations to extract information on the victim's access patterns. For example, in evict+ reload …
Transient-Execution Attacks: A Computer Architect Perspective
Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …
level. These optimizations are meant to be invisible to the programmer but they are implicitly …
Microarchitectural attacks in heterogeneous systems: A survey
With the increasing proliferation of hardware accelerators and the predicted continued
increase in the heterogeneity of future computing systems, it is necessary to understand the …
increase in the heterogeneity of future computing systems, it is necessary to understand the …
Improving cache management policies using dynamic reuse distances
Cache management policies such as replacement, bypass, or shared cache partitioning
have been relying on data reuse behavior to predict the future. This paper proposes a new …
have been relying on data reuse behavior to predict the future. This paper proposes a new …
PACMan: prefetch-aware cache management for high performance caching
Hardware prefetching and last-level cache (LLC) management are two independent
mechanisms to mitigate the growing latency to memory. However, the interaction between …
mechanisms to mitigate the growing latency to memory. However, the interaction between …