[HTML][HTML] Terahertz metadevices for silicon plasmonics
Metamaterial devices (metadevices) have been developed in progress aiming to generate
extraordinary performance over traditional devices in the (sub-) terahertz (THz) domain, and …
extraordinary performance over traditional devices in the (sub-) terahertz (THz) domain, and …
Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources
The research and development on solid‐state source generators have been making
progress on chip, aiming to generate low noise, high output power, and high DC‐to‐RF …
progress on chip, aiming to generate low noise, high output power, and high DC‐to‐RF …
A 25.8-GHz integer-N CPPLL achieving 60-fs rms jitter and robust lock acquisition based on a time–amplifying phase–frequency detector
This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With
the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is …
the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is …
A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop
PP Chary, R Shaik Peerla, A Dutta - Journal of Low Power Electronics and …, 2024 - mdpi.com
This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop
(PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A …
(PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A …
Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature]
Fast settling phase locked loops (PLLs) play a pivotal role in many applications requiring
rapid attainment of a stable frequency and phase. In modern communication standards …
rapid attainment of a stable frequency and phase. In modern communication standards …
A 21.8–41.6-GHz Low Jitter and High FoM $ _ {\bm {j}} $ Fast-Locking Subsampling PLL With Dead Zone Automatic Controller
In this article, a wideband millimeter-wave (mm-wave) fast-locking subsampling phase-
locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM) is proposed …
locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM) is proposed …
A 27.2–31.2 GHz 92-fs rms Integrated Jitter, Fractional-N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS
This article presents a fractional-subsampling PLL (FN-SSPLL) with a phase rotation (PR)
technique. The proposed PR-based FN-SSPLL has high output frequency resolution, low …
technique. The proposed PR-based FN-SSPLL has high output frequency resolution, low …
On-chip SRR and CSRR for millimeter-wave integrated systems: Review and applications
On-chip metadevices have been developed in progress aiming to generate extraordinary
performance over conventional components in millimeter-wave (mmW) realms, and their full …
performance over conventional components in millimeter-wave (mmW) realms, and their full …
[HTML][HTML] Design of fully differential fast SCL Schmitt-trigger delay element with tunable delay and hysteresis in design and run-time
S Pahlavan, MB Ghaznavi-Ghoushchi… - … , Devices, Circuits and …, 2023 - Elsevier
Tuning the delay of the circuit during the circuit performance can give a chance to a circuit to
reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting …
reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting …
A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur− 81.1 dBc in 0.13 μm CMOS technology
J Li, B Sun, J Huang, H Chang, R Jia… - International Journal of …, 2023 - Wiley Online Library
This paper presents a wide‐band charge‐pump phase‐locked loop (CPPLL) with reference
spur reduction techniques. To broaden the frequency range without deteriorating phase …
spur reduction techniques. To broaden the frequency range without deteriorating phase …