Weighted spin torque nano-oscillator system for neuromorphic computing
Neuromorphic computing is a promising strategy to overcome fundamental limitations, such
as enormous power consumption, by massive parallel data processing, similar to the brain …
as enormous power consumption, by massive parallel data processing, similar to the brain …
An input signal dependent 8-to-12 bit variable resolution SAR ADC with digitally implemented bit enhancement Logic
N Kandpal, A Singh, A Agarwal - AEU-International Journal of Electronics …, 2023 - Elsevier
This paper presents variable resolution SAR ADC with digitally implemented Bit
enhancement logic. Unlike conventional approaches, this work avoids complex hardware …
enhancement logic. Unlike conventional approaches, this work avoids complex hardware …
An improved strong arm comparator with integrated static preamplifier
This paper presents a novel Strong Arm comparator in which the input pair is reused as a
static amplifier to preamplify the input signal during the precharge phase. The proposed …
static amplifier to preamplify the input signal during the precharge phase. The proposed …
Cascode cross-coupled stage high-speed dynamic comparator in 65 nm CMOS
Dynamic comparators are the core of high-speed, high-resolution analog-to-digital
converters (ADCs) used for communication applications. Most of the dynamic comparators …
converters (ADCs) used for communication applications. Most of the dynamic comparators …
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces
This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4)
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …
A rail-to-rail high speed continuous time comparator for ToF application
R Tu, S Wu, Q Chen, Y Gong, J **e, J Li… - IEICE Electronics …, 2023 - jstage.jst.go.jp
The ToF system has a wide range of applications, including automatic driving, 3D
reconstruction, and intelligent robot navigation, and more. However, implementing time-of …
reconstruction, and intelligent robot navigation, and more. However, implementing time-of …
A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator
Y Cho, J Lee, S Park, S Yoo… - IEEE Journal of Solid-State …, 2024 - ieeexplore.ieee.org
This work presents a multiplying delay-locked loop (MDLL) that can generate an ultralow
jitter output signal,, at a very high output frequency,. Conventional MDLLs are limited in …
jitter output signal,, at a very high output frequency,. Conventional MDLLs are limited in …
Triple-Tail Common-Mode Insensitive High-Speed Dynamic Comparator for Analog In-Memory Computing Architectures
Analog in-memory computing architectures demand high-speed analog-to-digital
converters, for which a dynamic comparator is a crucial building block. Speed and common …
converters, for which a dynamic comparator is a crucial building block. Speed and common …
Robust body biasing techniques for dynamic comparators
Forward body biasing (FBB) is among the simplest and most effective techniques that can be
leveraged to improve the performance of dynamic comparators, as previous works have …
leveraged to improve the performance of dynamic comparators, as previous works have …
Body Biasing Techniques for Dynamic Comparators: A Systematic Survey
Forward body biasing (FBB) has often been exploited in the literature for improving the
performance of both analog and digital building blocks. Recent works have explored the …
performance of both analog and digital building blocks. Recent works have explored the …