Solving the third-shift problem in IC piracy with test-aware logic locking
The increasing IC manufacturing cost encourages a business model where design houses
outsource IC fabrication to remote foundries. Despite cost savings, this model exposes …
outsource IC fabrication to remote foundries. Despite cost savings, this model exposes …
Secure scan and test using obfuscation throughout supply chain
X Wang, D Zhang, M He, D Su… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Scan-based test is commonly used to increase testability and fault coverage, however, it is
also known to be a liability for chip security. Research has shown that intellectual property …
also known to be a liability for chip security. Research has shown that intellectual property …
Static and dynamic obfuscations of scan data against scan-based side-channel attacks
A Cui, Y Luo, CH Chang - IEEE Transactions on Information …, 2016 - ieeexplore.ieee.org
Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has
been widely used by cryptographic ICs to provide high fault coverage. Full controllability and …
been widely used by cryptographic ICs to provide high fault coverage. Full controllability and …
Novel test-mode-only scan attack and countermeasure for compression-based scan architectures
Scan design is a de facto design-for-testability (DfT) technique that enhances access during
manufacturing test process. However, it can also be used as a back door to leak secret …
manufacturing test process. However, it can also be used as a back door to leak secret …
A survey on security threats and countermeasures in IEEE test standards
The growth in complexity of Integrated Circuits (IC) is supported, amongst other factors, by
the development of standardized test infrastructures. The feasibility of both end …
the development of standardized test infrastructures. The feasibility of both end …
Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain
D Zhang, M He, X Wang… - 2017 IEEE 35th VLSI Test …, 2017 - ieeexplore.ieee.org
Scan-based test is commonly used to increase testability and fault coverage, however, it is
also known to be a liability for chip security. Research has shown that intellectual property …
also known to be a liability for chip security. Research has shown that intellectual property …
Scaling the effective area of higher-order-mode erbium-doped fiber amplifiers
We demonstrate scaling of the effective area of higher-order mode, Er-doped fiber
amplifiers. Two Er-doped higher-order mode fibers, one with 3800 μm^ 2 A_eff in the LP_0 …
amplifiers. Two Er-doped higher-order mode fibers, one with 3800 μm^ 2 A_eff in the LP_0 …
Ensuring cryptography chips security by preventing scan-based side-channel attacks with improved DFT architecture
W Wang, X Wang, J Wang, NN **ong… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Cryptography chips are often used in some applications, such as smart grids and Internet of
Things (IoT) to ensure their security. Cryptographic chips must be strictly tested to guarantee …
Things (IoT) to ensure their security. Cryptographic chips must be strictly tested to guarantee …
Security analysis of scan obfuscation techniques
Scan is the de-facto standard for testing, which provides high observability and test
coverage by enabling direct access to chip memory elements. The scan-based Design-for …
coverage by enabling direct access to chip memory elements. The scan-based Design-for …
Hardware Root of Trust for SSN-basedDFT Ecosystems
A hardware root of trust (RoT) is the foundation on which all secure operations of a circuit
depend, including those related to DFT. Despite many countermeasures aimed at facing …
depend, including those related to DFT. Despite many countermeasures aimed at facing …