T-CREST: Time-predictable multi-core architecture for embedded systems

M Schoeberl, S Abbaspour, B Akesson… - Journal of Systems …, 2015 - Elsevier
Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …

Contention in multicore hardware shared resources: Understanding of the state of the art

G Fernandez, J Abella, E Quiñones… - … Workshop on Worst …, 2014 - hal.science
The real-time systems community has over the years devoted considerable attention to the
impact on execution timing that arises from contention on access to hardware shared …

SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip

HMG Wassel, Y Gao, JK Oberg, T Huffmire… - ACM SIGARCH …, 2013 - dl.acm.org
As multicore processors find increasing adoption in domains such as aerospace and
medical devices where failures have the potential to be catastrophic, strong performance …

Global and local consistent age generative adversarial networks

P Li, Y Hu, Q Li, R He, Z Sun - 2018 24th International …, 2018 - ieeexplore.ieee.org
Age progression/regression is a challenging task due to the complicated and non-linear
transformation in human aging process. Many researches have shown that both global and …

Patmos: A time-predictable microprocessor

M Schoeberl, W Puffitsch, S Hepp, B Huber… - Real-Time …, 2018 - Springer
Current processors provide high average-case performance, as they are optimized for
general purpose computing. However, those optimizations often lead to a high worst-case …

Nocalert: An on-line and real-time fault detection mechanism for network-on-chip architectures

A Prodromou, A Panteli, C Nicopoulos… - 2012 45th Annual …, 2012 - ieeexplore.ieee.org
The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …

Interpret: a time-predictable multicore processor

ER Jellum, S Lin, P Donovan, C Jerad… - Proceedings of Cyber …, 2023 - dl.acm.org
With the end of Moore's law and the breakdown of Dennard scaling, multicore processors
are the standard way to continue improving performance while reducing Size, Weight and …

[HTML][HTML] Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs

P Andreu, S Alcaide, P Lopez, J Abella… - Future Generation …, 2025 - Elsevier
The increased performance requirements of applications running on safety-critical systems
have led to the use of complex platforms with several CPUs, GPUs, and AI accelerators …

An area-efficient network interface for a TDM-based network-on-chip

J Sparsø, E Kasapaki… - 2013 Design, Automation & …, 2013 - ieeexplore.ieee.org
Network interfaces (NIs) are used in multi-core systems where they connect processors,
memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The …

[PDF][PDF] A time-predictable memory network-on-chip

M Schoeberl, DV Chong, W Puffitsch… - … Workshop on Worst …, 2014 - drops.dagstuhl.de
To derive safe bounds on worst-case execution times (WCETs), all components of a
computer system need to be time-predictable: the processor pipeline, the caches, the …