T-CREST: Time-predictable multi-core architecture for embedded systems
Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …
execution time (WCET). Standard multi-core processors are optimized for the average case …
Contention in multicore hardware shared resources: Understanding of the state of the art
The real-time systems community has over the years devoted considerable attention to the
impact on execution timing that arises from contention on access to hardware shared …
impact on execution timing that arises from contention on access to hardware shared …
SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip
As multicore processors find increasing adoption in domains such as aerospace and
medical devices where failures have the potential to be catastrophic, strong performance …
medical devices where failures have the potential to be catastrophic, strong performance …
Global and local consistent age generative adversarial networks
Age progression/regression is a challenging task due to the complicated and non-linear
transformation in human aging process. Many researches have shown that both global and …
transformation in human aging process. Many researches have shown that both global and …
Patmos: A time-predictable microprocessor
Current processors provide high average-case performance, as they are optimized for
general purpose computing. However, those optimizations often lead to a high worst-case …
general purpose computing. However, those optimizations often lead to a high worst-case …
Nocalert: An on-line and real-time fault detection mechanism for network-on-chip architectures
The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …
criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming …
Interpret: a time-predictable multicore processor
With the end of Moore's law and the breakdown of Dennard scaling, multicore processors
are the standard way to continue improving performance while reducing Size, Weight and …
are the standard way to continue improving performance while reducing Size, Weight and …
[HTML][HTML] Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs
The increased performance requirements of applications running on safety-critical systems
have led to the use of complex platforms with several CPUs, GPUs, and AI accelerators …
have led to the use of complex platforms with several CPUs, GPUs, and AI accelerators …
An area-efficient network interface for a TDM-based network-on-chip
Network interfaces (NIs) are used in multi-core systems where they connect processors,
memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The …
memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The …
[PDF][PDF] A time-predictable memory network-on-chip
To derive safe bounds on worst-case execution times (WCETs), all components of a
computer system need to be time-predictable: the processor pipeline, the caches, the …
computer system need to be time-predictable: the processor pipeline, the caches, the …