Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology
E Mani, E Abbasian, M Gunasegeran… - … -International Journal of …, 2022 - Elsevier
Many researchers are trying to create a low power, high stability, and high-speed static
random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 …
random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 …
A reconfigurable 16Kb AND8T SRAM macro with improved linearity for multibit compute-in memory of artificial intelligence edge devices
Compute-in Memory (CIM) has been a promising candidate to perform the energy-efficient
multiply-and-accumulate (MAC) operations of the modern Artificial Intelligence (AI) edge …
multiply-and-accumulate (MAC) operations of the modern Artificial Intelligence (AI) edge …
Design of soft-error resilient SRAM cell with high read and write stability for robust operations
This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-
16T) to provide complete resilience to single event upsets (SEU). The proposed cell is …
16T) to provide complete resilience to single event upsets (SEU). The proposed cell is …
A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications
In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to
reducing power and energy consumption can show high reliability and have the least error …
reducing power and energy consumption can show high reliability and have the least error …
A 64 Kb reconfigurable full-precision digital ReRAM-based compute-in-memory for artificial intelligence applications
This work presents a fully-digital 64 Kb non-volatile ReRAM based compute-in-memory
(CIM) macro for the modern artificial intelligence (AI) edge devices, using 65 nm technology …
(CIM) macro for the modern artificial intelligence (AI) edge devices, using 65 nm technology …
Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design
Graphene nanoribbon and transition metal dichalcogenide field‐effect transistors (GNRFETs
and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide …
and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide …
Energy-efficient and variability-resilient 11T SRAM design using data-aware read–write assist (DARWA) technique for low-power applications
The need for power-efficient devices, such as smart sensor nodes, mobile devices, and
portable digital gadgets, is markedly increasing and these devices are becoming commonly …
portable digital gadgets, is markedly increasing and these devices are becoming commonly …
One-sided Schmitt-Trigger-based low power read decoupled 11T CNTFET SRAM with improved stability
The power requirements of wireless sensor networks and internet of things (IoT) applications
heavily rely on batteries. It is crucial that the memory cells utilized in these applications must …
heavily rely on batteries. It is crucial that the memory cells utilized in these applications must …
Design and investigation of stability‐and power‐improved 11T SRAM cell for low‐power devices
E Abbasian, S Birla… - International Journal of …, 2022 - Wiley Online Library
The modern system‐on‐chips require stable and low‐power SRAM cells due to technology
scaling and limited sources of energy. Therefore, a stability‐and power‐improved 11T …
scaling and limited sources of energy. Therefore, a stability‐and power‐improved 11T …
A 9T high-stable and low-energy half-select-free SRAM cell design using TMDFETs
The revolution in technology is so fast that even silicon devices are not able to meet the
current demand of high speed, low power, and minimal area. The CMOS SRAM cells are the …
current demand of high speed, low power, and minimal area. The CMOS SRAM cells are the …