This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …

In this Colloquium the theory of silicon nanowires is reviewed. Nanowires with diameters
below 10 nm are the focus, where quantum effects become important and the properties …

Semiconducting carbon nanotubes, and nanowires are potential alternatives to planar metal-
oxide-semiconductor field-effect transistors (MOSFETs) owing, for example, to their unique …

This paper provides an industry perspective on atomic layer etching (ALEt) process. Two
process sequences representing two different methods of ALEt are described, followed by …

We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at
300 K based on the Kubo-Greenwood formula and the self-consistent solution of the …

The role of dimensionality on the electronic performance of thermoelectric devices is
clarified using the Landauer formalism, which shows that the thermoelectric coefficients are …

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method
on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts …

Atomically thin two-dimensional (2D) semiconductors—particularly transition metal
dichalcogenides—are potential channel materials for post-silicon complementary metal …

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have
emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices …

Based on the real-space finite-difference method, we have developed a first-principles
density functional program that efficiently performs large-scale calculations on massively …