Predicting inter-thread cache contention on a chip multi-processor architecture

D Chandra, F Guo, S Kim… - … Symposium on High …, 2005 - ieeexplore.ieee.org
This paper studies the impact of L2 cache sharing on threads that simultaneously share the
cache, on a chip multi-processor (CMP) architecture. Cache sharing impacts threads …

Estimating cache misses and locality using stack distances

C CaΒcaval, DA Padua - Proceedings of the 17th annual international …, 2003 - dl.acm.org
Cache behavior modeling is an important part of modern optimizing compilers. In this paper
we present a method to estimate the number of cache misses, at compile time, using a …

Data cache locking for higher program predictability

X Vera, B Lisper, J Xue - ACM SIGMETRICS Performance Evaluation …, 2003 - dl.acm.org
Caches have become increasingly important with the widening gap between main memory
and processor speeds. However, they are a source of unpredictability due to their …

[PDF][PDF] A survey on static cache analysis for real-time systems

M Lv, N Guan, J Reineke, R Wilhelm… - Leibniz Transactions on …, 2016 - ojs.dagstuhl.de
Real-time systems are reactive computer systems that must produce their reaction to a
stimulus within given time bounds. A vital verification requirement is to estimate the Worst …

Fast data-locality profiling of native execution

E Berg, E Hagersten - Proceedings of the 2005 ACM SIGMETRICS …, 2005 - dl.acm.org
Performance tools based on hardware counters can efficiently profile the cache behavior of
an application and help software developers improve its cache utilization. Simulator-based …

Generating cache hints for improved program efficiency

K Beyls, EH D'Hollander - Journal of Systems Architecture, 2005 - Elsevier
One of the new extensions in EPIC architectures are cache hints. On each memory
instruction, two kinds of hints can be attached: a source cache hint and a target cache hint …

Analytical modeling of cache behavior for affine programs

W Bao, S Krishnamoorthy, LN Pouchet… - Proceedings of the …, 2017 - dl.acm.org
Optimizing compilers implement program transformation strategies aimed at reducing data
movement to or from main memory by exploiting the data-cache hierarchy. However, instead …

An analytical model for performance and lifetime estimation of hybrid DRAM-NVM main memories

R Salkhordeh, O Mutlu, H Asadi - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Emerging Non-Volatile Memories (NVMs) have promising advantages (eg, lower idle power,
higher density, and non-volatility) over the existing predominant main memory technology …

A fast analytical model of fully associative caches

T Gysi, T Grosser, L Brandner, T Hoefler - Proceedings of the 40th ACM …, 2019 - dl.acm.org
While the cost of computation is an easy to understand local property, the cost of data
movement on cached architectures depends on global state, does not compose, and is hard …

Bounding worst-case data cache behavior by analytically deriving cache reference patterns

H Ramaprasad, F Mueller - 11th ieee real time and embedded …, 2005 - ieeexplore.ieee.org
While caches have become invaluable for higher-end architectures due to their ability to
hide, in part, the gap between processor speed and memory access times, caches (and …