SystemC-link: Parallel SystemC simulation using time-decoupled segments
JH Weinstock, R Leupers, G Ascheid… - … , Automation & Test …, 2016 - ieeexplore.ieee.org
Virtual platforms have become essential tools in the design process of modern embedded
systems. Their accessibility and early availability make them ideal tools for design space …
systems. Their accessibility and early availability make them ideal tools for design space …
A new parallel SystemC kernel leveraging manycore architectures
The complexity of system-level modeling is continuously increasing. Electronic System Level
(ESL) design requires fast simulation techniques to control future SoC development cost and …
(ESL) design requires fast simulation techniques to control future SoC development cost and …
Parallel SystemC simulation for ESL design
Virtual platforms have become essential tools for the design of embedded systems.
Developers rely on them for design space exploration and software debugging. However …
Developers rely on them for design space exploration and software debugging. However …
Challenges for the parallelization of loosely timed SystemC programs
D Becker, M Moy, J Cornet - 2015 International Symposium on …, 2015 - ieeexplore.ieee.org
SystemC/TLM models are commonly used in the industry to provide an early SoC simulation
environment. The open source implementation of the SystemC simulator is sequential. The …
environment. The open source implementation of the SystemC simulator is sequential. The …
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models
To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market
constraints, Virtual Prototy** (VP) tools based on SystemC/TLM must get faster while …
constraints, Virtual Prototy** (VP) tools based on SystemC/TLM must get faster while …
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models
SystemC TLM-2.0 is currently the industry standard for simulating full Systems-on-a-Chip
(SoCs). Although SystemC is designed to simulate the behavior of complex, parallel …
(SoCs). Although SystemC is designed to simulate the behavior of complex, parallel …
Simian integrated framework for parallel discrete event simulation on GPUs
Discrete Event Simulation (DES) allows the modelling of ever more complex systems in a
variety of domains ranging from biological systems to road networks. The increasing need to …
variety of domains ranging from biological systems to road networks. The increasing need to …
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support
To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market
constraints, Virtual Prototy** (VP) tools based on SystemC/TLM2. 0 must get faster while …
constraints, Virtual Prototy** (VP) tools based on SystemC/TLM2. 0 must get faster while …
Parallel simulation of loosely timed systemC/TLM programs: challenges raised by an industrial case study
D Becker, M Moy, J Cornet - Electronics, 2016 - mdpi.com
Transaction level models of systems-on-chip in SystemC are commonly used in the industry
to provide an early simulation environment. The SystemC standard imposes coroutine …
to provide an early simulation environment. The SystemC standard imposes coroutine …
A parallel systemc virtual platform for neuromorphic architectures
With the increasing interest in neuromorphic computing, designers of embedded systems
face the challenge of efficiently simulating such platforms to enable architecture design …
face the challenge of efficiently simulating such platforms to enable architecture design …