[BOEK][B] VLSI test principles and architectures: design for testability

LT Wang, CW Wu, X Wen - 2006 - books.google.com
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Embedded deterministic test

J Rajski, J Tyszer, M Kassab… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
This paper presents a novel test-data volume-compression methodology called the
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …

[BOEK][B] Electronic design automation: synthesis, verification, and test

LT Wang, YW Chang, KTT Cheng - 2009 - books.google.com
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

[BOEK][B] System-on-chip test architectures: nanometer design for testability

LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

Embedded deterministic test for low cost manufacturing test

J Rajski, J Tyszer, M Kassab… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper introduces embedded deterministic test (EDT) technology, which reduces
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …

A unified approach to reduce SOC test data volume, scan power and testing time

A Chandra, K Chakrabarty - IEEE transactions on computer …, 2003 - ieeexplore.ieee.org
We present a test resource partitioning (TRP) technique that simultaneously reduces test
data volume, test application time, and scan power. The proposed approach is based on the …

Extending relational database systems to automatically enforce privacy policies

R Agrawal, P Bird, T Grandison… - … Conference on Data …, 2005 - ieeexplore.ieee.org
Databases are at the core of successful businesses. Due to the voluminous stores of
personal data being held by companies today, preserving privacy has become a crucial …

Nine-coded compression technique for testing embedded cores in SoCs

M Tehranipoor, M Nourani… - IEEE transactions on …, 2005 - ieeexplore.ieee.org
This paper presents a new test-data compression technique that uses exactly nine
codewords. Our technique aims at precomputed data of intellectual property cores in system …

Extending opmisr beyond 10/spl times/scan test efficiency

C Barnhart, V Brunkhorst, F Distler… - IEEE Design & Test …, 2002 - ieeexplore.ieee.org
Extending OPMISR beyond 10/spl times/ scan test efficiency Page 1 65 0740-7475/02/$17.00 ©
2002 IEEE September–October 2002 SCAN-BASED LOGIC TESTING using auto- matic …

RL-Huffman encoding for test compression and power reduction in scan applications

M Nourani, MH Tehranipour - ACM Transactions on Design Automation …, 2005 - dl.acm.org
This article mixes two encoding techniques to reduce test data volume, test pattern delivery
time, and power dissipation in scan test applications. This is achieved by using run-length …