According to one general aspect, an apparatus may include a host interface circuit
configured to receive a memory access request, wherein the memory access request is …

In some implementations, the present disclosure relates to a method. The method includes
obtaining a set of weights for a neural network comprising a plurality of nodes and a plurality …

An error detection and correction method for a flash memory includes: a setting step, setting
selection information to select a first error detection and correction function for performing 1 …

A non-volatile storage apparatus comprises a plurality of memory cells that store host data
and two models, a control circuit for writing to and reading from the memory cells, and an …

Noise injection procedures implemented on the die of a non-volatile memory (NVM) array
are disclosed. In one example, noise is injected into data by adjusting read voltages to …

An apparatus includes a first encoder circuit configured to compress a block of data using
dictionary based compression and a second encoder circuit connected to the first encoder …

A non-volatile storage apparatus comprises one or more memory die assemblies, each of
which includes an inference circuit positioned in the memory die assembly. The inference …

Apparatuses and methods can be related to implementing age-based network training. An
artificial neural network (ANN) can be trained by introducing errors into the ANN. The errors …

Latch-based methods and apparatus for performing neural network weight parity detection
on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network …

Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile
memory (NVM) array are disclosed. The exemplary latch-based MAC procedures described …