This paper presents a comprehensive survey of existing techniques for interconnect
optimization during the VLSI physical design process, with emphasis on recent studies on …

In this paper, we study the optimal wiresizing problem under the Elmore delay model. We
show that the optimal wiresizing solutions satisfy a number of interesting properties …

In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two
objective functions: i) delay minimization only, or ii) combined delay and power dissipation …

In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay
and power dissipation minimization. We prove the BS/WS relation for optimal SBWS …

23 Design Automation Conference, 1986, pp. 708–714. Fang, S. et al., Constrained Via
Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Prob lems, 28." …

In this paper, we propose an eflicient timing-driven global routing algorithm. Unlike other
conventional global routing techniques, interconnection delays are modeled and included …

US6738960B2 - Method and apparatus for producing sub-optimal routes for a net by generating
fake configurations - Google Patents US6738960B2 - Method and apparatus for producing …

In this paper, we study the optimal wiresizing problem for nets with multiple sources under
the RC tree model and the Elmore delay model. We decompose the routing tree for a …

US7080336B2 - Method and apparatus for computing placement costs - Google Patents
US7080336B2 - Method and apparatus for computing placement costs - Google Patents Method …

4,593,363 A 6/1986 Burstein et al. particular net in the region, the method then identifies a
route 4,615,011 A 9/1986 Linsker that connects the Sub-regions that contains a pin from the …