Software-controlled fault tolerance
Traditional fault-tolerance techniques typically utilize resources ineffectively because they
cannot adapt to the changing reliability and performance demands of a system. This paper …
cannot adapt to the changing reliability and performance demands of a system. This paper …
Cache aware optimization of stream programs
J Sermulins, W Thies, R Rabbah… - Proceedings of the 2005 …, 2005 - dl.acm.org
Effective use of the memory hierarchy is critical for achieving high performance on
embedded systems. We focus on the class of streaming applications, which is increasingly …
embedded systems. We focus on the class of streaming applications, which is increasingly …
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing
A El-Haj-Mahmoud, AS Al-Zawawi… - Proceedings of the …, 2005 - dl.acm.org
The design of a real-time architecture is governed by a trade-off between analyzability
necessary for real-time formalism and performance demanded by high-end embedded …
necessary for real-time formalism and performance demanded by high-end embedded …
Parallel repetition of zero-knowledge proofs and the possibility of basing cryptography on np-hardness
R Pass - 21st Annual IEEE Conference on Computational …, 2006 - ieeexplore.ieee.org
Two long-standing open problems exist on the fringe of complexity theory and
cryptography:(1) Does there exist a reduction from an NP-complete problem to a one-way …
cryptography:(1) Does there exist a reduction from an NP-complete problem to a one-way …
Deep Jam: Conversion of coarse-grain parallelism to instruction-level and vector parallelism for irregular applications
A number of compute-intensive applications suffer from performance loss due to the lack of
instruction-level parallelism in sequences of dependent instructions. This is particularly …
instruction-level parallelism in sequences of dependent instructions. This is particularly …
Software thread integration for hardware to software migration
AG Dean - 2000 - search.proquest.com
This dissertation introduces software thread integration (STI) and its use for migrating
functions from hardware to software (HSM). STI interleaves multiple software threads at the …
functions from hardware to software (HSM). STI interleaves multiple software threads at the …
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
A El-Haj-Mahmoud, E Rotenberg - Proceedings of the 2004 international …, 2004 - dl.acm.org
A coarse-grain multithreaded processor can effectively hide long memory latencies by
quickly switching to an alternate task when the active task issues a memory request …
quickly switching to an alternate task when the active task issues a memory request …
Hardware to software migration with real-time thread integration
Introduces thread integration, a new method of providing low-cost concurrency for
microcontrollers and microprocessors. This post-pass compiler technology effectively …
microcontrollers and microprocessors. This post-pass compiler technology effectively …
Extending sti for demanding hard-real-time systems
B Welch, S Kanaujia, A Seetharam… - Proceedings of the …, 2003 - dl.acm.org
Software thread integration (STI) is a compilation technique which enables the efficient use
of an application's fine-grain idle time on generic processors without special hardware …
of an application's fine-grain idle time on generic processors without special hardware …
Enhancing the AvrX kernel with efficient secure communication using software thread integration
P Ganesan, AG Dean - … . RTAS 2004. 10th IEEE Real-Time and …, 2004 - ieeexplore.ieee.org
We present methods to add efficient cryptographic support to low-performance embedded
processors with embedded networks (eg sensor networks). Software thread integration (STI) …
processors with embedded networks (eg sensor networks). Software thread integration (STI) …