Incremental delta-sigma ADCs: A tutorial review
In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key
block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such …
block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such …
Trending IC design directions in 2022
For the non-stop demands for a better and smarter society, the number of electronic devices
keeps increasing exponentially; and the computation power, communication data rate, smart …
keeps increasing exponentially; and the computation power, communication data rate, smart …
Jitter-power trade-offs in PLLs
B Razavi - IEEE Transactions on Circuits and Systems I …, 2021 - ieeexplore.ieee.org
As new applications impose jitter values in the range of a few tens of femtoseconds, the
design of phase-locked loops faces daunting challenges. This paper derives basic relations …
design of phase-locked loops faces daunting challenges. This paper derives basic relations …
A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion
A interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages
the performance advantages of ring amplifiers to unlock greater architectural freedom. The …
the performance advantages of ring amplifiers to unlock greater architectural freedom. The …
A 6.4-GS/s 1-GHz BW continuous-time pipelined ADC with time-interleaved sub-ADC-DAC achieving 61.7-dB SNDR in 16-nm FinFET
We introduce a continuous-time (CT) pipeline analog-to-digital converter (ADC) featuring a
time-interleaved sub-ADC-digital-to-analog converter (DAC) path in its first stage. The …
time-interleaved sub-ADC-digital-to-analog converter (DAC) path in its first stage. The …
A 1-MS/s to 1-GS/s ringamp-based pipelined ADC with fully dynamic reference regulation and stochastic scope-on-chip background monitoring in 16 nm
This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference
buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of …
buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of …
A 4-GS/s 11.3-mW 7-bit time-based ADC with folding voltage-to-time converter and pipelined TDC in 65-nm CMOS
A folding voltage-to-time converter (VTC) is proposed for low-power time-based (TB) flash
ADCs performing voltage-to-time-to-digital conversion. Conventional VTCs in TB flash ADCs …
ADCs performing voltage-to-time-to-digital conversion. Conventional VTCs in TB flash ADCs …
A 2-GS/s time-interleaved ADC with embedded background calibrations and a novel reference buffer for reduced inter-channel crosstalk
Time-interleaved (TI) analog-to-digital converters (ADCs) are an established architecture,
but fundamental problems still exist that prevent replicating the performance of each sub …
but fundamental problems still exist that prevent replicating the performance of each sub …
A 12-bit 1 GS/s RF sampling pipeline-SAR ADC with harmonic injecting cross-coupled pair achieving 7.5 fj/conv-step
We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register
(SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross …
(SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross …
Lower bounds on power consumption of clock generators for ADCs
B Razavi - 2020 IEEE International Symposium on Circuits and …, 2020 - ieeexplore.ieee.org
This paper formulates the jitter-power trade-offs in the design of phase-locked loops that
provide the sampling clock for ADCs. We obtain lower bounds for the oscillator power …
provide the sampling clock for ADCs. We obtain lower bounds for the oscillator power …