A conventional Network-on-Chip (NoC) router uses input buffers to store in-flight packets.
These buffers improve performance, but consume significant power. It is possible to bypass …

One of the promising usages of Physically Unclonable Functions (PUFs) is to generate
cryptographic keys from PUFs for secure storage of key material. This usage has attractive …

In this paper we propose a new congestion-aware routing algorithm. At the First step, this
algorithm splits NoC into a number of subnets. Then a global routing algorithm within each …

Congestion-aware routing algorithms attempt to have more diversity in routes to be chosen
and avoid congested areas in networks-on-chip. In this paper, a novel fully adaptive …

The growing demand of computing power and the emerging trend towards heterogeneity
lead to integrate more and more cores and specialized modules into a single chip. As the …

In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property
(IP) cores are integrated to reinforce parallel processing and high performance computing …

Many-core chip designs are the current manufacturing trend for high-performance
computing. Different challenges lead to different designs, whether general purpose-driven …

Conventional theory for designing strictly nonblocking networks, such as crossbars or Clos
networks, assumes that these networks have a centralized topology. Many new applications …

In this paper, we propose a novel distributed source-throttling congestion control mechanism
for bufferless NoC, called Cbufferless. Our strategy uses a novel congestion detection and …

As the number of core integration on a single die grows, buffers consume significant energy,
and occupy chip area. A bufferless deflection routing that eliminates router's input-port …