An increase in demand for semiconductor ICs, recent advancements in machine learning,
and the slowing down of Moore's law have all contributed to the increased interest in using …

Hardware Description Language (HDL) is a common entry point for designing digital circuits.
Differences in HDL coding styles and design choices may lead to considerably different …

In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where
designers define precise design behavior with hardware description languages (HDLs) like …

In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are
performed only after physical synthesis. Encountered timing violations cause re-iterations of …

In modern VLSI design flow, evaluating the quality of register-transfer level (RTL) designs
involves time-consuming logic synthesis using electronic design automation tools, a process …

This paper discloses a Reinforcement Learning (RL) solution implemented to decrease the
peak current by alteration of the clock skews. Clock skews are elements of the clock network …

Nowadays, the digital chip design flow starts with formal specifications, which are mapped to
Register Transfer Level (RTL) models using different underlying (micro-) architectures. By …

Embedded systems are becoming increasingly complex, which has led to a productivity
crisis in their design and verification. Although conventional design automation coupled with …

Accurate timing information of a digital design is available only after routing. Timing
violations require corrective changes, even at the register-transfer level (RTL). Thus, timing …

In chip design, it is crucial to identify timing critical components early on to preemptively fix
any timing issues and avoid numerous design convergence iterations. However, obtaining …