DAOmap: A depth-optimal area optimization map** algorithm for FPGA designs
In This work we study the technology map** problem for FPGA architectures to minimize
chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip …
chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip …
Low-power technology map** for FPGA architectures with dual supply voltages
In this paper we study the technology map** problem of FPGA architectures with dual
supply voltages (Vdds) for power optimization. This is done with the guarantee that the …
supply voltages (Vdds) for power optimization. This is done with the guarantee that the …
GlitchMap: An FPGA technology mapper for low power considering glitches
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and
signal glitches contribute a large portion of the dynamic power consumption. Previous power …
signal glitches contribute a large portion of the dynamic power consumption. Previous power …
Technology map** and clustering for FPGA architectures with dual supply voltages
This paper presents a technology map** algorithm for field-programmable gate array
architectures with dual supply voltages (Vdds) for power optimization. This is done with the …
architectures with dual supply voltages (Vdds) for power optimization. This is done with the …
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
V Garg, V Chandrasekhar, M Sashikánth… - Proceedings of the 2005 …, 2005 - dl.acm.org
The main objective of the technique presented in this paper is to exploit the relations
between a set of Boolean functions so as to generate one function from another. The paper …
between a set of Boolean functions so as to generate one function from another. The paper …
[LIVRE][B] Efficient Runtime Management of Reconfigurable Hardware Resources.
T Marconi - 2011 - researchgate.net
Runtime reconfigurable systems built upon devices with partial recon-figuration can provide
reduction in overall hardware area, power efficiency, and economic cost in addition to the …
reduction in overall hardware area, power efficiency, and economic cost in addition to the …
Power optimization of LUT based FPGA circuits
M Mashayekhi, Z Jeddi, E Amini - 2008 11th International …, 2008 - ieeexplore.ieee.org
In this paper, a new method for decreasing the power consumption in LUT based FPGA
circuits is presented that attempts to reduce the switching activity among LUT blocks. To …
circuits is presented that attempts to reduce the switching activity among LUT blocks. To …
Sa based power efficient FPGA LUT map**
R Dobson, K Steinhöfel - Proceedings of the 15th annual conference …, 2013 - dl.acm.org
Look up Table (LUT) based Field Programmable Gate Arrays (FPGAs) are commonly used
in mobile devices due to their efficient signal processing capabilities and flexibility to be …
in mobile devices due to their efficient signal processing capabilities and flexibility to be …
SETmap: A soft error tolerant map** algorithm for FPGA designs with low power
Field programmable gate arrays (FPGAs) are widely used in VLSI applications due to their
flexibility to implement logical functions, fast total turn-around time and low none-recurring …
flexibility to implement logical functions, fast total turn-around time and low none-recurring …
[PDF][PDF] A Novel Logic Element for Power Reduction in FPDs
Although many techniques have been proposed for power reduction in fieldprogrammable
devices (FPDs), they are all based on conventional logic elements (LEs). In the conventional …
devices (FPDs), they are all based on conventional logic elements (LEs). In the conventional …