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A Review of Integrated Systems and Components for 6G Wireless Communication in the D-Band
T Maiwald, T Li, GR Hotopan, K Kolb… - Proceedings of the …, 2023 - ieeexplore.ieee.org
The evolution of wireless communication points to increasing demands on throughput for
data-intensive applications in modern society. Integrated millimeter-wave systems with …
data-intensive applications in modern society. Integrated millimeter-wave systems with …
Oscillator flicker phase noise: A tutorial
A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in
supporting ultra-low PN frequency generation for the advanced communications and other …
supporting ultra-low PN frequency generation for the advanced communications and other …
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
W Wu, CW Yao, C Guo, PY Chiang… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
This work presents a low-spur and low-jitter fractional-digital phase-locked loop (PLL). To
reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC) …
reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC) …
A harmonic-mixing PLL architecture for millimeter-wave application
A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by
the invariably large closed-loop gain and the high operation frequency of the voltage …
the invariably large closed-loop gain and the high operation frequency of the voltage …
A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance
With the rapid development of the modern communication technology, the communication
standards impose stringent performance requirements, such as the ultra-low jitter …
standards impose stringent performance requirements, such as the ultra-low jitter …
A millimeter-wave CMOS VCO featuring a mode-ambiguity-aware multi-resonant-RLCM tank
This paper presents a millimeter-wave NMOS-PMOS-complementary (CMOS) VCO with a
multi-resonant Resistor-Inductor-Capacitor-Mutual Inductance (RLCM) tank. It features an 8 …
multi-resonant Resistor-Inductor-Capacitor-Mutual Inductance (RLCM) tank. It features an 8 …
32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS
E Thaller, R Levinger, E Shumaker… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
The demand for massive MIMO, digital beamforming, and increased bandwidth
communication dramatically increases the complexity of the remote radio head in future …
communication dramatically increases the complexity of the remote radio head in future …
A low-jitter and low-spur charge-sampling PLL
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL).
A charge-domain sub-sampling phase detector is introduced to achieve a high phase …
A charge-domain sub-sampling phase detector is introduced to achieve a high phase …