As the trends of process scaling make memory systems an even more crucial bottleneck, the
importance of latency hiding techniques such as prefetching grows further. However, naively …

Past research has proposed numerous hardware prefetching techniques, most of which rely
on exploiting one specific type of program context information (eg, program counter …

This paper presents Voyager, a novel neural network for data prefetching. Unlike previous
neural models for prefetching, which are limited to learning delta correlations, our model can …

Applications extensively use data objects with a regular and fixed layout, which leads to the
recurrence of access patterns over memory regions. Spatial data prefetching techniques …

This paper introduces the Irregular Stream Buffer (ISB), a prefetcher that targets irregular
sequences of temporally correlated memory references. The key idea is to use an extra level …

Irregular workloads are typically bottlenecked by the memory system. These workloads often
use sparse data representations, eg, compressed sparse row/column (CSR/CSC), to …

Hardware prefetching is an effective technique for hiding cache miss latencies in modern
processor designs. Prefetcher performance can be characterized by two main metrics that …

Data prefetching, ie, the act of predicting an application's future memory accesses and
fetching those that are not in the on-chip caches, is a well-known and widely used approach …

Big-data server applications frequently encounter data misses, and hence, lose significant
performance potential. One way to reduce the number of data misses or their effect is data …

Prefetching is a well-studied technique for addressing the memory access stall time of
contemporary microprocessors. However, despite a large body of related work, the memory …